ApplySarthiPerl jobs in Austin
141 open roles in Austin asking for Perl, at 15 companies, from company job boards. Newest first; open a listing to apply on the employer's own site.
This market right now
Who is hiring: Amazon (44), Nvidia (35), Intel (12), Annapurna Labs (9), Cadence (8), Nxp (8), Amazon Web Services (5), Marvell (5) and others.
What Perl roles in Austin keep asking for: Python (74%), C++ (46%), Java (28%), C# (22%), Linux (16%), Shell scripting (13%) — counted across the newest postings here.
Perl jobs elsewhere
- All Perl jobs2,214 open
- Perl jobs in the United States1370 open
- Perl jobs in Seattle360 open
- Perl jobs in India343 open
- Perl jobs in Bengaluru224 open
- Perl jobs in New York67 open
- Perl jobs in San Jose64 open
- Perl jobs in Hyderabad63 open
- Perl jobs in Singapore53 open
- Perl jobs in the United Kingdom39 open
- Perl jobs in China37 open
- Perl jobs in Canada37 open
- Perl jobs in Ireland32 open
- Perl jobs in Germany31 open
- Perl jobs in Australia30 open
- Perl jobs in Dublin28 open
- Perl jobs in Pune27 open
- Perl jobs in Taiwan26 open
- Perl jobs in Malaysia23 open
- Perl jobs in Toronto22 open
- Perl jobs in Boston22 open
- Perl jobs in London21 open
- Perl jobs in Israel20 open
- Perl jobs in Dallas20 open
- Perl jobs in Sunnyvale19 open
- Perl jobs in Berlin15 open
- Perl jobs in Delhi NCR14 open
- Perl jobs in Mexico12 open
- Perl jobs in San Francisco11 open
- Perl jobs in San Diego10 open
- Remote Perl jobs37 open
Find the jobs that fit your CV
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Find jobs that fit my CV- SDE II, AVMSAmazon · US, TX, Austin · 2026-11-13
- 2027 SARC/ACL R&D Internship Program – Multiple Engineering TeamsSec · 3900 N Capital of Texas Hwy, Austin, TX, USA, 3655 N 1st St, San Jose, CA, USA · 2026-11-13
- DFT EngineerBroadcom · USA-TX-Austin - River Place B6 · 2026-11-12
- Security Engineer II–AMZ011502Amazon · US, TX, Austin · 2026-11-10
- RTL Design EngineerIntel · US, Texas, Austin, US, Arizona, Phoenix, US, Oregon, Hillsboro · 2026-11-10
- Senior Design Verification EngineerIntel · US, Texas, Austin, US, California, Santa Clara, US, Arizona, Phoenix · 2026-11-10
- Junior CPU Verification EngineerIntel · US, Texas, Austin, US, Oregon, Hillsboro · 2026-11-10
- RF Comms Systems Engineer, Amazon LeoAmazon · US, TX, Austin · 2026-11-09
- Lead Design EngineerCadence · AUSTIN · 2026-11-07
- SDEII Specialist GenAI Tooling, Specialist Technology Team (STT), AWS WWSO SA Field InitiativesAmazon Web Services · US, TX, Austin · 2026-11-06
- Software Dev Engineer, Amazon Leo Customer Terminal SoftwareAmazon · US, TX, Austin · 2026-11-06
- Senior Compute Platform Engineer, LSF - EDA InfrastructureNvidia · US, CA, Remote, US, TX, Austin, US, Remote · 2026-11-06
- DFT EngineerBroadcom · USA-TX-Austin - River Place B6 · 2026-11-06
- DFT Lead EngineerBroadcom · USA-TX-Austin - River Place B6 · 2026-11-06
- Sr Principal Application EngineerCadence · AUSTIN · 2026-11-06
- STA Application EngineerCadence · SAN JOSE, AUSTIN · 2026-11-06
- EDA Tool Software EngineerIntel · US, Texas, Austin, US, Oregon, Hillsboro, US, California, Folsom, US, California, Santa Clara · 2026-11-03
- EDA Tool Software EngineerIntel · US, Texas, Austin, US, Oregon, Hillsboro, US, California, Folsom, US, California, Santa Clara · 2026-11-03
- Senior Verification Engineer - CPUNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-11-03
- Compiler Verification Engineer, Compute Performance – GPUNvidia · US, TX, Austin, US, CA, Santa Clara · 2026-11-03
- Software Development Engineer, AWS InspectorAmazon · US, TX, Austin · 2026-11-02
- Memory Design EngineerIntel · US, Texas, Austin · 2026-11-02
- IC design Implementation and SignOff Architect, (STA SignOff)Cadence · HOME OR, SEATTLE 01, TORONTO 02, HOME SD, HOME CA, SAN JOSE, AUSTIN · 2026-11-02
- Principal AE (STA - SignOff)Cadence · AUSTIN · 2026-11-02
- Senior ASIC Verification EngineerNvidia · US, TX, Austin · 2026-10-30
- Senior GPU PCIe and Boot ArchitectNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- Senior GPU Architect, Deep LearningNvidia · US, CA, Santa Clara, US, TX, Austin, US, NC, Durham · 2026-10-30
- Senior Physical Design EngineerNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- EDA Methodology ArchitectNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- Senior Power Analysis and Optimization EngineerNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- Senior Formal Verification EngineerNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- Senior Verification Engineer - CPUNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- Senior GPU ArchitectNvidia · US, CA, Santa Clara, US, MA, Westford, US, TX, Austin, US, NC, Durham · 2026-10-30
- Senior ASIC Floorplan Design EngineerNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- ASIC Physical Design Engineer, Netlisting - New College Grad 2026Nvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- ASIC Design Engineer - HardwareNvidia · US, TX, Austin · 2026-10-30
- Senior ASIC Floorplan Design EngineerNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- Senior ASIC Physical Design Engineer, NetlistingNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- Senior Memory System ArchitectNvidia · US, CA, Santa Clara, US, TX, Austin, US, NC, Durham · 2026-10-30
- Senior ASIC Design Verification Infrastructure and Tools Engineer – GPUNvidia · US, CA, Santa Clara, US, MA, Westford, US, TX, Austin, US, NC, Durham, US, CA, Remote · 2026-10-30
- Senior ASIC Verification Engineer - HSIONvidia · US, MA, Westford, US, TX, Austin · 2026-10-30
- GPU PCIe and Boot Architect - New College Grad 2027Nvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- Senior Mask Layout Design EngineerNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- PCIe Design Verification Intern - Summer 2027Nvidia · US, TX, Austin · 2026-10-30
- Senior Full-Chip RTL Integration EngineerNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- Senior DTCO Engineer, CPU Physical DesignNvidia · US, CA, Santa Clara, US, TX, Austin, US, OR, Hillsboro, US, NC, Durham · 2026-10-30
- Senior Physical Design Methodology Engineer, PPA Improvement Technology ScalingNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-10-30
- Senior SRAM Engineer, Circuit DesignNvidia · US, CA, Santa Clara, US, TX, Austin, US, TX, Remote, US, CA, Remote · 2026-10-30
- Software Dev Engineer II, Amazon KeyAmazon · US, TX, Austin · 2026-10-29
- SDE II, AVMS, AVMSAmazon · US, TX, Austin · 2026-10-29
- CPU Physical Design EngineerIntel · US, Texas, Austin · 2026-10-29
- SRAM/ROM Circuit Design EngineerNxp · Austin (Oakhill, Office) · 2026-10-29
- Software Development Engineer II, AVMS, AVMSAmazon · US, TX, Austin · 2026-10-27
- Software Dev Engineer II - AMZ26886.2Amazon Web Services · US, TX, Austin · 2026-10-27
- Software Dev Engineer II - AMZ27610.1Amazon · US, TX, Austin · 2026-10-27
- Software Development Engineer II, CLS Infrastructure and Product SecurityAmazon · US, TX, Austin · 2026-10-26
- Static Timing Analysis Design Engineer / Physical DesignNxp · Austin (Oakhill, Office) · 2026-10-24
- Senior Staff Engineer, Physical DesignMarvell · Austin, TX · 2026-10-22
- Software Development Engineer, Amazon Customer ServiceAmazon · US, TX, Austin · 2026-10-20
- Entry Level DFT Design EngineerNxp · Austin (Oakhill, Office) · 2026-10-20
- Chip Lead / Physical Design DirectorCadence · AUSTIN 03, SAN JOSE · 2026-10-20
- Network Development Engineer, IRGAmazon · US, TX, Austin · 2026-10-15
- Network Development Engineer, IRGAmazon · US, TX, Austin · 2026-10-15
- Software Development Engineer, Customer Experience Improvement - Defect EnrichmentAmazon · US, TX, Austin · 2026-10-15
- Software Dev Engineer, Amazon Leo Customer Terminal SoftwareAmazon · US, TX, Austin · 2026-10-15
- Software Dev Engineer, Amazon Leo Customer Terminal SoftwareAmazon · US, TX, Austin · 2026-10-15
- Software Dev Engineer, Amazon Leo Customer Terminal SoftwareAmazon · US, TX, Austin · 2026-10-15
- Software Dev Engineer, Amazon Leo Customer Terminal SoftwareAmazon · US, TX, Austin · 2026-10-15
- Software Dev Engineer, Amazon Leo Customer Terminal SoftwareAmazon · US, TX, Austin · 2026-10-15
- IA Core Post Silicon Validation EngineerIntel · US, Texas, Austin · 2026-10-14
- CPU Verification EngineerIntel · US, Texas, Austin · 2026-10-14
- AI-Driven Physical Design Engineering (PhD Intern)Intel · US, California, Santa Clara, US, Colorado, Fort Collins, US, Massachusetts, Beaver Brook, US, Oregon, Hillsboro, US, Texas, Austin · 2026-10-14
- Pre-Silicon Verification EngineerIntel · US, Oregon, Hillsboro, US, Massachusetts, Beaver Brook, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin, US, Arizona, Phoenix · 2026-10-14
- Sr. EDA Tools Engineer - PERC ESDIntel · US, Oregon, Hillsboro, US, California, Santa Clara, US, Texas, Austin, US, Arizona, Phoenix · 2026-10-14
- Marketing SpecialistCgm · Austin · 2026-10-14
- Verification Engineer IINxp · Austin (Oakhill, Office) · 2026-10-14
- Static Timing Analysis Design Engineer / Physical DesignNxp · Austin (Oakhill, Office) · 2026-10-14
- Static Timing Analysis Design Engineer / Physical DesignNxp · Austin (Oakhill, Office) · 2026-10-14
- IC CAD EngineerBroadcom · USA-AZ-Chandler-North Juniper Drive, USA-California-San Jose-1320 Ridder Park Drive, USA-TX-Austin - River Place B7, USA-CA-San Diego-West Bernardo, USA-CA Irvine Alton Parkway Bldg 1 · 2026-10-14
- Senior Analog/Mixed-Signal (AMS) Design Verification EngineerAnalogdevices · US, TX, Austin, Plaza on the Lake, US, NC, Durham · 2026-10-14
- Product Engineer II, ConformalCadence · SAN JOSE, AUSTIN · 2026-10-14
- Design Verification Architect / DirectorCadence · SAN JOSE, AUSTIN · 2026-10-14
- Design Verification Intern, BS - Summer 2027Marvell · Santa Clara, CA, Austin, TX, Westborough, MA, Boise, ID, Morrisville, NC · 2026-10-12
- Design Verification Intern, MS - Summer 2027Marvell · Santa Clara, CA, Austin, TX, Westborough, MA, Boise, ID, Morrisville, NC · 2026-10-12
- Digital IC Design Intern, BS - Summer 2027Marvell · Santa Clara, CA, Irvine, CA, Austin, TX, US-NY - Hudson Valley, Boise, ID · 2026-10-12
- Digital IC Design Intern, MS - Summer 2027Marvell · Santa Clara, CA, Irvine, CA, Austin, TX, US-NY - Hudson Valley, Boise, ID · 2026-10-12
- Software Developer 3Oracle · Austin, TX, United States, Nashville, TN, United States, United States · 2026-10-08
- Principal Physical Design EngineerNxp · Austin (Oakhill, Office) · 2026-10-08
- SoC Validation EngineerNxp · Austin (Oakhill, Office) · 2026-10-08
- Software Development Engineer, Platform Engineering and Services (AFT Labor Insights)Amazon · US, TX, Austin · 2026-10-06
- Data Scientist , Reactive TransfersAmazon · US, TX, Austin · 2026-10-06
- Principal SLT Test EngineerGraphcore · Austin, Texas, United States · 2026-10-06
- Network Development Engineer II, Satellite Systems Integration and Test, Amazon LeoAmazon · US, TX, Austin · 2026-10-05
- ASIC Design Engineer, Tools and Methodology DevelopmentNvidia · US, TX, Austin · 2026-10-02
- MLA Design Verification Engineer, Annapurna LabsAnnapurna Labs · US, TX, Austin · 2026-09-29
- GPU PCIe and Boot Architect - New College Grad 2026Nvidia · US, CA, Santa Clara, US, TX, Austin · 2026-09-29
- MLA IP Design Verification Engineer, Annapurna LabsAnnapurna Labs · US, TX, Austin · 2026-09-28
- Custom SOC IP Verification EngineerNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-09-26
- Custom SOC IP Verification EngineerNvidia · US, CA, Santa Clara, US, TX, Austin · 2026-09-26
- Cloud Hardware Development Engineer I, Annapurna Labs, Early Career - 2027Annapurna Labs · US, TX, Austin · 2026-09-24
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