Design Verification Architect / Director
Cadence
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This role on the market
537 open verification roles across 51 companies are on ApplySarthi right now, most of them in Bengaluru (112), Hyderabad (53), Pune (9).
- Staff System Engineer, Integration & VerificationJobgether
- Head of Formal Verification (m/f/d)Lubis Eda
- ASIC Design Verification Engineer, Amazon LeoAmazon Kuiper Manufacturing Enterprises LLC
- Verification EngineerIMC
- Hardware (PCBA) Design and Verification Intern (Winter 2027 - 4 months)Ciena
What verification roles keep asking for: Python (18%) — counted across their open postings here.
Cadence has 623 open roles listed here.
- RTL2GDS, Product Engineering Architect
- Lead Red Hat Linux Architect
- Sr. Interface IC, IP Sales Executive II
- IT, Enterprise, Infrastructure Architect
- Software Engineer II: Hardware Verification Compiler
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for verification roles keep coming back to Python. Practise those questions before you sit with Cadence.
Questions you are likely to be asked
- Why do you want to join Cadence?
- What is your experience with Linux? Tell me one thing you learned the hard way.
- How do you balance what users ask for with what the business needs?
- Walk me through a design from your portfolio, from the problem to the result.
- Tell me about design feedback you disagreed with. What happened?
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Practise the Design Verification Architect / Director at Cadence interview free →At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Location San Jose, CA and Austin, TX Job Description Responsibilities As a Design Verification Team Director, lead and run the Processor Verification team, you will be responsible for the verification of microprocessor cores and their peripherals Relevant experience in-order/out-of-order CPU cores and memory subsystem strongly preferred Crafting verification plans and executing them to verify highly complex CPU designs. You will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will be responsible for coverage collection and closure You will work closely with cross-functional teams (DV/Arch/Design/FW) to identify coverage scope Tracking and reporting the work of 7-10 engineers Required Skills and Experience: 17+ years of design verification experience BS (or higher) in EE/Computer Engineering Proven experience at leading/managing team. Strong managerial, leadership and interpersonal skills Excellent knowledge of computer architecture and design verification fundamentals Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches Exposure to scripting languages like Perl, Unix shell or similar languages Experience with assembly language programming required Experience with Formal Verification will be a plus Experience with the development of fully automated flows Experience with Gate Level Simulations Excellent written and oral communication skills necessary Knowledge of processor verification required The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.
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Listed on workday · posted 2026-09-16. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.