Senior Lead Engineer - STA
Nxp
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This role on the market
47 open sta roles across 10 companies are on ApplySarthi right now, most of them in Bengaluru (9), Hyderabad (2), Pune (1).
- Design Implementation Engineer (Synthesis / STA)Broadcom
- STA Application EngineerCadence
- Senior STA EngineerNvidia
- (staż) Inżynier ds. Przygotowania Danych Aplikacyjnych (Customer Application Engineer)Hitachi
- Staff STA EngineerAnalogdevices · bengaluru
What sta roles keep asking for: Python (45%), Perl (34%) — counted across their open postings here.
Nxp has 810 open roles listed here.
- Senior Cyber Threat Intelligence Analyst
- Learning Management Systems Specialistbengaluru
- Technical Director, SoC Architectpune
- Senior Product Engineer - Secure Transactions & Identification (m/f/d)
- Etch Equipment Engineer
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for sta roles keep coming back to Python, Perl. Practise those questions before you sit with Nxp.
Questions you are likely to be asked
- Why do you want to join Nxp?
- Tell me about a hard bug you tracked down. How did you find the cause?
- How do you decide what to test, and what does good code review look like to you?
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
- How would you design an API for a feature you have worked on?
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Practise the Senior Lead Engineer - STA at Nxp interview free →The Digital Physical Design Engineer is responsible for complete STA signoff for the SOC or Subsystem. The individual is responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write correct constraints, refining constraints throughout SOC design cycle and constraints validation. The individual must have exposure of AI and use AI in STA activities. The individual is responsible for complete timing signoff till the tapeout for subsystem or full chip. Must have leading capabilities on signoff function. Must have worked on SDF generation and validation. Must have all knowledge of SI closure. Must have exposure to higher tech nodes such as 16nm and 5nm. Must be conversant with physical design flows and functions and must possess good knowledge of placement, CTS and Routing. The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node. More information about NXP in India... #LI-2734
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Listed on workday · posted 2026-10-08. ApplySarthi collects openings and links to application pages; the role is advertised by Nxp, not by us.