Senior STA Engineer
Nvidia
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This role on the market
47 open sta roles across 10 companies are on ApplySarthi right now, most of them in Bengaluru (9), Hyderabad (2), Pune (1).
- Design Implementation Engineer (Synthesis / STA)Broadcom
- STA Application EngineerCadence
- (staż) Inżynier ds. Przygotowania Danych Aplikacyjnych (Customer Application Engineer)Hitachi
- Staff STA EngineerAnalogdevices · bengaluru
What sta roles keep asking for: Python (45%), Perl (34%) — counted across their open postings here.
Nvidia has 3,820 open roles listed here.
- Software Developer - Networking
- Manager, Silicon Circuit and Power Integrity - Silicon Co-Design Group
- Senior Physical Design Methodology Engineerbengaluru
- Electro Optics Student
- Manager, Software Verification
Counted across 14 company job boards, updated as roles open and close.
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Interviews for sta roles keep coming back to Python, Perl. Practise those questions before you sit with Nvidia.
Questions you are likely to be asked
- Why do you want to join Nvidia?
- What is your experience with Perl? Tell me one thing you learned the hard way.
- What do you do when a production issue happens on your code?
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
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Practise the Senior STA Engineer at Nvidia interview free →NVIDIA is seeking a Physical Design and Timing Engineer to join our silicon implementation team. This role focuses on timing analysis, timing closure, and signoff quality across complex ASIC and SoC designs. You will work closely with physical design, front-end design, methodology, and CAD teams to drive robust implementation at advanced process nodes. This is a strong fit for an engineer who enjoys deep analysis, problem solving, and improving quality at block and full-chip levels. What you’ll be doing: Drive static timing analysis and timing closure for block and/or full-chip designs. Develop, review, and debug timing constraints, scenarios, and signoff checks. Analyze setup, hold, noise, and variation-related timing issues and drive closure with cross-functional teams. Partner with physical design engineers on floorplan, CTS, route, ECO, and convergence activities. Review reports, identify root causes of violations, and recommend high-quality fixes with minimal design impact. Improve timing methodology, automation, and debug efficiency using Tcl, Perl, and/or Python. What we need to see: B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience. 5+ years of experience in ASIC or SoC physical design, timing analysis, or implementation. Strong understanding of static timing analysis fundamentals, timing constraints, and timing closure. Hands-on experience with industry-standard EDA tools such as PrimeTime, ICC2, Innovus, Tempus, or equivalent. Experience debugging setup/hold violations, clocking issues, and ECO impacts. Solid scripting skills in Tcl plus familiarity with Perl or Python. Good communication skills and ability to work across design, CAD, and verification teams. Ways to stand out from the crowd: Experience with advanced-node implementation and signoff. Knowledge of MMMC flows, SI, OCV/AOCV/POCV, and power-aware timing analysis. Experience improving timing methodology or developing reusable automation. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided a reasonable accommodation to participate in the job application or interview process, perform essential job functions, and receive other benefits and privileges of employment. Please contact us to request accommodation.
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Listed on workday · posted 2026-11-02. ApplySarthi collects openings and links to application pages; the role is advertised by Nvidia, not by us.