Senior ASIC Design Engineer
Nvidia
Nvidia is also hiring for this role in US, CA, Santa Clara, US, CA, Santa Clara, US, CA, Santa Clara, US, CA, Santa Clara, US, CA, Remote, US, CA, Santa Clara, US, NC, Durham.
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This role on the market
3,614 open design roles across 340 companies are on ApplySarthi right now, most of them in Bengaluru (325), Hyderabad (124), Chennai (52).
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What design roles keep asking for: Python (20%) — counted across their open postings here.
Asic Design Engineer jobs in the United States · C++ jobs · Perl jobs · Python jobs
Nvidia has 3,820 open roles listed here.
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Counted across 14 company job boards, updated as roles open and close.
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Practise the Senior ASIC Design Engineer at Nvidia interview free →We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing! What you'll be doing: As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications. Analyze architectural trade-offs based on features, performance requirements and system limitations. Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. Work on a broad list of IPs such as GPU's work scheduler, time distribution system, interrupt controllers, and DMA engines. Architect features to help silicon debug and support post-silicon validation activities. What we need to see: Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering or Computer Science. 8+ years of meaningful work experience. Experience in micro-architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic is required. Strong interpersonal skills and an excellent teammate. Ways to stand out from the crowd: Strong C/C++, Python or Perl skills. Good debugging and analytical skills. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until August 18, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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Listed on workday · posted 2026-10-30. ApplySarthi collects openings and links to application pages; the role is advertised by Nvidia, not by us.