Principal Design Engineer - Verification

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Design Engineer - Verification Location: Shanghai Job Responsibilities: Looking for a skilled VLSI Design Verification Engineer with 3–5 years of hands-on experience to join our team supporting SOC design projects for leading customers. The ideal candidate will collaborate closely with design and verification teams to ensure comprehensive test coverage, robust verification methodology, and seamless project execution. Will play a key role in bridging communication between local teams and global stakeholders. Hands-on experience in any protocol like AMBA, PCIe, USB, MIPI or DDR/LPDDR. ARM/RISC-V Processor integration experience preferred. Develop and execute verification plans for SOC and IP blocks, ensuring design intent and testability. Perform RTL verification using industry-standard methodologies (e.g., UVM, SystemVerilog). Collaborate with design engineers to address complex debug issues and optimize verification strategies. Work closely with customer and internal engineering teams to deliver high-quality support and service. Participate in coverage analysis, regression testing, and closure of verification goals. Contribute to the development and enhancement of verification environments and reusable testbenches. Requirements: Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field with 3–5 years of experience in VLSI/SOC design verification. Strong expertise in System Verilog, UVM, and Verification tools. We’re doing work that matters. Help us solve what others can’t.