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Design Engineer II

Cadence

Cadence is also hiring for this role in Nanjing, AUSTIN, Hyderabad, Delhi NCR, SHANGHAI, Bengaluru.

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This role on the market

3,625 open design roles across 340 companies are on ApplySarthi right now, most of them in Bengaluru (325), Hyderabad (124), Chennai (52).

What design roles keep asking for: Python (20%) — counted across their open postings here.

Design Engineer jobs in Bengaluru · Design Engineer jobs in India · Remote Design Engineer jobs · C++ jobs · Python jobs

Cadence has 700 open roles listed here.

Counted across 14 company job boards, updated as roles open and close.

Preparing for this interview

Interviews for design roles keep coming back to Python. Practise those questions before you sit with Cadence.

Questions you are likely to be asked

  1. Why do you want to join Cadence?
  2. What is your experience with C++? Tell me one thing you learned the hard way.
  3. Tell me about a hard bug you tracked down. How did you find the cause?
  4. How do you decide what to test, and what does good code review look like to you?
  5. Describe a time a deadline forced a trade-off in quality. What did you choose and why?

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Minimum Qualifications: 2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc Preferred Qualifications: Experience managing small teams (at least 2 members and above) Experience leading the complete post silicon validation efforts for at least one full project 1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug. Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL Experience conducting hiring interviews and mentoring new hires BE/BTech/ME/MTech or equivalent We’re doing work that matters. Help us solve what others can’t.

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Listed on workday · posted 2026-10-12. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.