ApplySarthiSoC Physical Design Engineer
Nokia
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Skills named in this job
Read from the description itself, not inferred.
This role on the market
314 open physical roles across 68 companies are on ApplySarthi right now, most of them in Bengaluru (15), Pune (7), Hyderabad (3).
- Advanced R&D - Physical Design EngineerKandou Ai
- Product Manager - Physical AIAnybotics
- Physical Security Architect, Data Center EngineeringAmazon Web Services Singapore Private Limited
- Applied Scientist- Physical AI for Manufacturing, OMHS SCSAmazon.com Services LLC - A57
- Physical Design Engineer, Amazon LeoAmazon Kuiper Manufacturing Enterprises LLC
What physical roles keep asking for: Python (16%) — counted across their open postings here.
Nokia has 617 open roles listed here.
- Sr. Product Test Capability Engineer
- Staff QA Engineer
- Optical Engineer
- Staff Optical Engineer
- Principal QA Engineer
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for physical roles keep coming back to Python. Practise those questions before you sit with Nokia.
Questions you are likely to be asked
- Why do you want to join Nokia?
- What is your experience with Perl? Tell me one thing you learned the hard way.
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
- How do you decide what to test, and what does good code review look like to you?
Prep Sarthi gives you a free mock interview: an AI interviewer asks you questions like these out loud, from your own CV and this job, and shows your score and your weakest answer.
Practise the SoC Physical Design Engineer at Nokia interview free →You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow, doing implementation to achieve best in class ASICs, which are optimized for power, performance and area metrics. NION2026 3+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design Experience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar, PV tools like Calibre and IR tools like Redhawk Scripting experience in TCL, python or Perl Candidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics
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Listed on oraclehcm · posted 2026-09-03. ApplySarthi collects openings and links to application pages; the role is advertised by Nokia, not by us.