Director, ASIC Physical Design

We are seeking an experienced and visionary Director of ASIC Physical Design to strategically lead and direct our global physical design engineering teams. This pivotal role involves driving the physical implementation of complex ASICs from RTL to GDSII, with a strong emphasis on achieving optimal performance, ultra-low power , and area (PPA) targets on the latest technology nodes . The successful candidate will be responsible for defining advanced physical design methodologies, managing and developing teams across the USA, India, and Italy , fostering innovation, and collaborating closely with cross-functional engineering groups to deliver high-quality, manufacturable silicon, ensuring first-pass success under aggressive schedules . Master's degree in Electrical Engineering, Computer Engineering, or a related field; Ph.D. preferred. 15+ years of progressive experience in ASIC physical design, with at least 8 years in a leadership or management role overseeing large, multi-site teams. Deep expertise in all aspects of the ASIC physical design flow, including floorplanning, power planning, placement, CTS, routing, timing closure, power analysis, and physical verification. Proven track record of successfully leading multiple complex ASIC tape-outs on advanced and latest technology nodes (e.g., 7nm, 5nm, 3nm and beyond), with significant experience in implementing and optimizing low-power design techniques. Demonstrated experience in introducing and deploying new physical design methodologies, including experience with CoT flow, leading to successful GDSII release. Strong command of industry-standard EDA tools from vendors such as Synopsys, Cadence, and Siemens EDA. Understanding of AI for Physical Design flow development & required automation. Understanding of Chip level IR analysis with required Package models. Exceptional leadership, communication, and interpersonal skills, with the ability to influence and drive results across diverse, geographically dispersed teams. Demonstrated ability to attract, develop, and retain top engineering talent globally. Preferred Qualifications: Experience with custom layout and mixed-signal integration. Familiarity with various memory compilers, SerDes, and other hard IP integration. Experience with design for testability (DFT) and design for manufacturing (DFM) considerations. Understanding of package and board-level interactions with silicon.