SoC verification

Accountabilities:: Take technical ownership of verification for 4–5 complex design blocks within each project and drive them toward verification sign-off. Build and maintain complete verification environments, including testbench infrastructure, agents, test sequences, scoreboards, and functional coverage models. Develop verification components from scratch using SystemVerilog and UVM. Execute directed and constrained-random testing across complex digital designs. Debug verification failures, analyze waveforms, investigate protocols, and perform root-cause analysis. Drive functional and code coverage closure and manage regression triage. Apply protocol knowledge to verify complex architectural features involving technologies such as UCIe, PCIe, and Ethernet. Collaborate with customer engineering teams and internal project leads to align block-level verification with top-level testbench infrastructure. Use industry-standard simulation tools to execute regressions and resolve verification issues efficiently. Contribute to high-quality verification sign-off for complex networking and interconnect ASIC designs. Requirements: 6–10+ years of hands-on ASIC verification experience involving complex digital designs. Expert-level proficiency in SystemVerilog and UVM, with demonstrated experience developing complete verification environments from scratch. Strong experience building testbenches, test sequences, agents, scoreboards, and other UVM components independently. Hands-on experience verifying at least one high-speed protocol such as UCIe 2.0, PCIe Gen 4/5/6, or Ethernet. Experience with complex networking silicon, switches, NICs, or high-performance interconnect ASICs. Strong expertise in waveform analysis, protocol debugging, root-cause analysis, and regression triage. Experience with simulators such as Synopsys VCS, Cadence Xcelium, or Mentor Questa. Strong understanding of functional and code coverage methodologies and verification closure. Excellent problem-solving and analytical skills, with the ability to investigate complex hardware verification issues. Strong communication and collaboration skills, with the ability to work autonomously in a customer-facing environment. UCIe, PCIe, and Ethernet protocol expertise is highly valuable, although end-to-end UVM expertise is the primary requirement. Benefits: Compensation of approximately $60–$80 per hour, depending on qualifications, experience, and location. Competitive compensation package for W2 employees. Healthcare insurance options, including medical, dental, and vision coverage. Major holidays. Paid sick leave in accordance with applicable state law. Remote work opportunity. Opportunity to work on complex ASIC verification and advanced networking silicon. Exposure to high-speed interconnect technologies and modern verification methodologies.