Senior Verification Design Automation Engineer

Accountabilities:: Develop, maintain, and continuously improve AI-based verification flows, infrastructure, automation frameworks, and execution environments used across block, subsystem, and SoC-level ASIC verification. Build and support scalable regression flows, dashboards, reporting utilities, and triage automation that improve verification productivity, visibility, and issue resolution. Create and enhance automation scripts, tools, integrations, and workflow utilities using Python, Perl, Tcl, shell scripting, Make, and related technologies. Support simulation, coverage, lint, formal, emulation, and continuous integration flows while partnering with verification, design, architecture, and CAD teams. Manage and troubleshoot compute, storage, licensing, queue, and job-dispatch infrastructure issues that affect verification execution and turnaround times. Drive automation improvements that make verification environments more reliable, reproducible, debuggable, scalable, and efficient across geographically distributed teams. Requirements: 8+ years of post-college experience in design automation, verification automation, CAD, infrastructure, ASIC verification support, or a closely related field. 8+ years of experience developing scripts and automation using Python, Perl, Tcl, shell scripting, or similar programming and automation languages. Strong experience supporting Linux-based engineering environments, source-control systems, build flows, regression execution, and EDA tool integrations. Proven ability to debug automation failures, tool and runtime issues, infrastructure bottlenecks, and workflow inefficiencies within complex verification environments. Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical discipline. Master’s degree in a related technical discipline is preferred. Experience with large-scale ASIC verification environments, regression farms, EDA tool flows, and distributed compute infrastructure is preferred. Knowledge of SystemVerilog and UVM verification methodologies, with the ability to collaborate effectively with verification engineers, is preferred. Experience with GitHub Actions, Git workflows, job schedulers, data analytics, regression management, coverage tracking, and productivity metrics is a plus. Benefits: Fully remote position for employees residing within the United States. Competitive total compensation package including cash compensation, equity, and performance-based incentives. Eligibility for performance-based incentives such as an annual bonus, depending on role. Medical, dental, and vision insurance. Disability and life insurance. Dependent care flexible spending account, accidental injury insurance, and pet insurance. Generous paid holidays and 401(k) with company match. Open Time Off (OTO) for regular full-time exempt employees. Additional paid time off benefits, including sick time, bonding leave, and pregnancy disability leave. Flexible work environment with opportunities to collaborate with leading organizations in the semiconductor industry. Equal opportunity workplace with accommodations available for qualified applicants throughout the recruitment and selection process.