ApplySarthi

Sr Principal Design Engineer

Cadence

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What design roles keep asking for: Python (20%) — counted across their open postings here.

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Questions you are likely to be asked

  1. Why do you want to join Cadence?
  2. What is your experience with Perl? Tell me one thing you learned the hard way.
  3. How would you design an API for a feature you have worked on?
  4. What do you do when a production issue happens on your code?
  5. Walk me through a system you built. How was it designed, and what would you change now?

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Responsibilities: Working in Cadence Flagship Emulation and Prototyping product line; Responsible for designing, developing, modifying and productizing protocol products like PCIe, advanced Ethernet and many more which are crucial to modern IC design and verification. Perform as individual contributor on protocol projects involving logic RTL design, UVM based verification, board design/debug and documentation etc. Work on complex problems related to protocol or system integration level issues, electrical or timing closure issues, RTL design or verification methodologies. Requirements: The position requires MSEE or equivalent, with experience in logic design and debug. Must have excellent communication skills, both written and verbal. RTL design experience using Verilog is required along with experience in using RTL verification tools and flows. Experience in FPGA design for Xilinx products is strongly recommended. UVM verification experience is desired. Experience with scripting languages like Perl, TCL C-shell is desired. We’re doing work that matters. Help us solve what others can’t.

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Listed on workday · posted 2026-10-13. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.