ApplySarthi

Sr Principal Design Engineer

Cadence

Tailor my CV for this job, freeView job and applyYour CV rewritten for this role, from your real experience. Sign in with Google, nothing to install.

Got this interview? Our apps help you get the job.

Prep SarthiFree 7-min demoPractise this interview with an AI interviewer, out loud.Unlimited mocks · ₹99/month →Live Sarthi30 min free demoAnswer hints during the real call, hidden from supported screen sharing.Unlimited interviews · ₹149/2 days · Windows →

This role on the market

3,693 open design roles across 350 companies are on ApplySarthi right now, most of them in Bengaluru (334), Hyderabad (124), Chennai (54).

What design roles keep asking for: Python (20%) — counted across their open postings here.

Design Engineer jobs in Bengaluru · Design Engineer jobs in India · Remote Design Engineer jobs

Cadence has 708 open roles listed here.

Counted across 14 company job boards, updated as roles open and close.

Preparing for this interview

Interviews for design roles keep coming back to Python. Practise those questions before you sit with Cadence.

Questions you are likely to be asked

  1. Why do you want to join Cadence?
  2. Describe a time a deadline forced a trade-off in quality. What did you choose and why?
  3. How would you design an API for a feature you have worked on?
  4. What do you do when a production issue happens on your code?
  5. Walk me through a system you built. How was it designed, and what would you change now?

Prep Sarthi gives you a free mock interview: an AI interviewer asks you questions like these out loud, from your own CV and this job, and shows your score and your weakest answer.

Practise the Sr Principal Design Engineer at Cadence interview free →

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Experience: 10- 15 years Location - Bangalore/Pune/ Responsibilities: · Complete DFT ownership of projects including: Test architecture definition. Identifying and implementing RTL changes for DFT. Performing scan insertion, LEC checks, low power CLP checks. Developing timing constraints for test mode timing closure. Scan and ATPG for different fault models. Boundary scan, ACJTAG, IEEE 1500 implementation and verification. IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests. Running zero delay and timing simulations and debugging on all the above aspects. Supporting post silicon bring up. Interacting with customers on DFT aspects and support Marketing & Pre-Sales team. Experience working on very high speed and low power designs. We’re doing work that matters. Help us solve what others can’t.

Match this job to your CV

ApplySarthi scores your CV against this role, shows the skills you are missing, and writes a tailored version for the application.

Check my match →

Similar open roles

Need answers during your interview? Try Live Sarthi.

Live Sarthi, an Interview Sarthi app, shows answer suggestions during the call.

Try Live Sarthi free →

A Windows app, from the same team as ApplySarthi.

Listed on workday · posted 2026-10-13. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.