ApplySarthiSr Principal Design Engineer
Cadence
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This role on the market
3,625 open design roles across 340 companies are on ApplySarthi right now, most of them in Bengaluru (325), Hyderabad (124), Chennai (52).
- Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine LearningAnnapurna Labs
- Electrical Design Engineer, APAC Data Center Design EngineeringAmazon · mumbai
- Tech Infra Program Manager II, Network Design and Deployment Team (NIDD) Amazon Web Services
- Senior Design EngineerCarrier · hyderabad
- Lead Design ResearcherJobgether
What design roles keep asking for: Python (20%) — counted across their open postings here.
Design Engineer jobs in Bengaluru · Design Engineer jobs in India · Remote Design Engineer jobs
Cadence has 700 open roles listed here.
- lead Design Engineerhyderabad
- Sr Financial Analyst
- Principal Business Operations Managerbengaluru
- Senior Systems Engineer (HPC/Server Farm)
- Senior Principal Application Engineer
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for design roles keep coming back to Python. Practise those questions before you sit with Cadence.
Questions you are likely to be asked
- Why do you want to join Cadence?
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
- How do you decide what to test, and what does good code review look like to you?
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
Prep Sarthi gives you a free mock interview: an AI interviewer asks you questions like these out loud, from your own CV and this job, and shows your score and your weakest answer.
Practise the Sr Principal Design Engineer at Cadence interview free →At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer 12+ years of Design Verification experience with SV/UVM Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. Design Verification experience verifying complex designs and leading projects from concept to verification closure. Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required. Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantag We’re doing work that matters. Help us solve what others can’t.
Match this job to your CV
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Listed on workday · posted 2026-10-12. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.