ApplySarthiSr Principal Design Engineer
Cadence
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Skills named in this job
Read from the description itself, not inferred.
This role on the market
3,625 open design roles across 340 companies are on ApplySarthi right now, most of them in Bengaluru (325), Hyderabad (124), Chennai (52).
- Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine LearningAnnapurna Labs
- Electrical Design Engineer, APAC Data Center Design EngineeringAmazon · mumbai
- Tech Infra Program Manager II, Network Design and Deployment Team (NIDD) Amazon Web Services
- Senior Design EngineerCarrier · hyderabad
- Lead Design ResearcherJobgether
What design roles keep asking for: Python (20%) — counted across their open postings here.
Design Engineer jobs in Bengaluru · Design Engineer jobs in India · Remote Design Engineer jobs · Perl jobs
Cadence has 700 open roles listed here.
- lead Design Engineerhyderabad
- Sr Financial Analyst
- Principal Business Operations Managerbengaluru
- Senior Systems Engineer (HPC/Server Farm)
- Senior Principal Application Engineer
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for design roles keep coming back to Python. Practise those questions before you sit with Cadence.
Questions you are likely to be asked
- Why do you want to join Cadence?
- What is your experience with Perl? Tell me one thing you learned the hard way.
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
- How do you decide what to test, and what does good code review look like to you?
Prep Sarthi gives you a free mock interview: an AI interviewer asks you questions like these out loud, from your own CV and this job, and shows your score and your weakest answer.
Practise the Sr Principal Design Engineer at Cadence interview free →At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently Should be good in Perl/Tcl scripting and automation We’re doing work that matters. Help us solve what others can’t.
Match this job to your CV
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Listed on workday · posted 2026-10-12. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.