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Sr. Lead ASIC design Engineer - Digital Design

Nxp

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  1. Why do you want to join Nxp?
  2. How would you design an API for a feature you have worked on?
  3. What do you do when a production issue happens on your code?
  4. Walk me through a system you built. How was it designed, and what would you change now?
  5. Tell me about a hard bug you tracked down. How did you find the cause?

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Key Responsibilities Define and implement hardware architectures optimized for AI inference SOC's Contribute to micro-architecture definition and evaluate design trade-offs for complex SOC including custom-ISA based processors, high-speed interconnects & high-bandwidth IO's Own features end-to-end: specification → RTL → integration → synthesis → debug Collaborate with physical design teams on synthesis, timing closure, and power optimization. Collaborate with verification team to ensure design correctness. Work with architect engineers to model workloads, analyze performance bottlenecks, and validate AI inference use cases. Required Qualifications 7+ years of experience in ASIC/SoC RTL design Strong Verilog/SystemVerilog coding skills Solid understanding of synthesis, timing, and power analysis Experience with Lint/CDC/RDC flows Strong debugging and root-cause analysis capability More information about NXP in India... #LI-2734

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Listed on workday · posted 2026-08-28. ApplySarthi collects openings and links to application pages; the role is advertised by Nxp, not by us.