Senior Physical Design Engineer
Nxp
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This role on the market
420 open physical roles across 60 companies are on ApplySarthi right now, most of them in Bengaluru (25), Pune (5), Hyderabad (5).
- Principal Analyst (Physical AI Semiconductors, IOT, Market Intelligence, Forecast/ Market Sizing models)Gartner
- Product Designer, Physical EngineeringOpenai
- Substation Physical Designer IIIJobgether
- Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine LearningAnnapurna Labs
- Physical Security Engineer (Design) , Data Center Engineering , Physical Security Architects - Design EngineeringAmazon
What physical roles keep asking for: Python (37%), Perl (19%) — counted across their open postings here.
Nxp has 810 open roles listed here.
- Senior Cyber Threat Intelligence Analyst
- Learning Management Systems Specialistbengaluru
- Technical Director, SoC Architectpune
- Senior Product Engineer - Secure Transactions & Identification (m/f/d)
- Etch Equipment Engineer
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for physical roles keep coming back to Python, Perl. Practise those questions before you sit with Nxp.
Questions you are likely to be asked
- Why do you want to join Nxp?
- What do you do when a production issue happens on your code?
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
- How do you decide what to test, and what does good code review look like to you?
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Practise the Senior Physical Design Engineer at Nxp interview free →Job Title: Senior Physical Design Engineer Location Pune / Bangalore / Hyderabad (Hybrid) Experience 8-10 Years Job Summary We are seeking a highly motivated and experienced Senior Physical Design Engineer to join our VLSI Physical Design team. The candidate will be responsible for delivering high-quality physical implementation of complex SoC/IP blocks from netlist to GDSII, ensuring timing, power, area, and reliability targets are met. The ideal candidate should have hands-on expertise in advanced node design implementation and signoff methodologies. Key Responsibilities Own end-to-end physical design implementation of complex digital blocks/subsystems. Drive floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification. Perform design optimization for PPA (Power, Performance, Area) targets. Execute timing closure across multiple operating modes and process corners. Analyze and resolve setup, hold, SI, IR-drop, EM, and congestion issues. Collaborate with RTL, Synthesis, DFT, STA, Package, and Signoff teams to achieve project milestones. Support ECO implementation and tapeout activities. Develop and enhance PD methodologies, automation flows, and scripts to improve productivity. Review design quality and mentor junior engineers. Work closely with global cross-functional teams. Required Technical Skills Strong expertise in: Floorplanning Power Planning Placement Optimization Clock Tree Synthesis (CTS) Routing Timing Closure Physical Verification STA & Signoff In-depth knowledge of: Static Timing Analysis (STA) Multi-Mode Multi-Corner (MMMC) methodologies Crosstalk/SI Analysis ECO Flows Timing Signoff Physical Signoff Experience with: IR Drop Analysis Electromigration (EM) Analysis DRC/LVS Closure Reliability Checks Tools Hands-on experience with industry-standard EDA tools: Cadence Innovus Synopsys ICC2 PrimeTime Tempus RedHawk / Voltus StarRC / Quantus Calibre Educational Qualification Bachelor's or Master's Degree in Electronics, VLSI, Electrical Engineering, or related field. More information about NXP in India... #LI-9415
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Listed on workday · posted 2026-10-08. ApplySarthi collects openings and links to application pages; the role is advertised by Nxp, not by us.