Principal DFT Engineer
Nxp
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This role on the market
135 open dft roles across 16 companies are on ApplySarthi right now, most of them in Bengaluru (26), Pune (4), Hyderabad (3).
- Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead)Boeing
- DFT Team ManagerBroadcom
- Design / DFT Director (NVE Engineering)Micron
- DFT ATPG EngineerNvidia
- Senior Principal Engineer-DFTMarvell
What dft roles keep asking for: Perl (54%), Python (51%), C++ (18%) — counted across their open postings here.
Dft Engineer jobs in the United States · iOS jobs
Nxp has 810 open roles listed here.
- Senior Cyber Threat Intelligence Analyst
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Counted across 14 company job boards, updated as roles open and close.
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- Why do you want to join Nxp?
- What is your experience with iOS? Tell me one thing you learned the hard way.
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
- How do you decide what to test, and what does good code review look like to you?
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Practise the Principal DFT Engineer at Nxp interview free →DFT Engineer You will join a team working on leading-edge projects in the Business Unit (BU) MCU & MPU Engineering & Design Enablement (MMEDE). MMEDE BU brings the technology and ecosystem relationships for next gen automotive Processing, Edge Processing & Radar Processing products. Your Responsibilities: Handling RTL Design for DFT related changes in both Subsystem level & Top level Designs. Inserting of MBIST RTL for memories & Verifying them. Analyzing Scan DRCs & fixing them in RTL. Analyzing ATPG reports on coverage & devise mechanism to improve coverage & generating patterns for ATE. Inserting of TAP, IOs, Test Pinmux using NXP DFT flows. Power Aware RTL/ GLS simulation bringup & taking care of the regression suite for both Non-ATPG & ATPG simulations. Bringing up Patterns on Wafer probe & on Final Test by working closely with Product & Test teams. Your Profile: DFT engineer with 5 + years of experience in DFT implementation and verification of scan architectures, JTAG, memory BIST, ATPG. Self-driven, results-oriented with a positive outlook, and a clear focus on high quality deliverables. Empathic communicator, able to see things from the other person's point of view. Should be willing to take up new challenges in the project and be a team player. The engineer should be well versed in Digital Design Concept, preferably having subject knowledge on Verilog/VHDL RTL coding. The candidate should preferably have experience in any one of the following areas. Scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Able to debug and root cause problems in simulation failures. More information about NXP in the United States... NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. #LI-6692
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Listed on workday · posted 2026-10-08. ApplySarthi collects openings and links to application pages; the role is advertised by Nxp, not by us.