ApplySarthiLead Software Engineer - Logic Synthesis
Cadence
Cadence is also hiring for this role in SHANGHAI.
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Skills named in this job
Read from the description itself, not inferred.
This role on the market
27 open synthesis roles across 15 companies are on ApplySarthi right now, most of them in Hyderabad (3), Bengaluru (3).
- ASIC Physical Design Engineer — Synthesis and Timing – (Associate or Experienced)Boeing
- Design Implementation Engineer (Synthesis / STA)Broadcom
- Director, Text-to-Speech Synthesis ResearchDeepgram
- Physical Design Engineer, Synthesis and ImplementationNvidia
- Synthesis Instrumentation EngineerAdaptyv
What synthesis roles keep asking for: Python (44%), Perl (26%), Excel (19%) — counted across their open postings here.
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Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for synthesis roles keep coming back to Python, Perl, Excel. Practise those questions before you sit with Cadence.
Questions you are likely to be asked
- Why do you want to join Cadence?
- What is your experience with C++? Tell me one thing you learned the hard way.
- How do you decide what to test, and what does good code review look like to you?
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
- How would you design an API for a feature you have worked on?
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Practise the Lead Software Engineer - Logic Synthesis at Cadence interview free →At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Description: Responsible for development and maintenance of the synthesizer for Palladium. Implementation for new VHDL/Verilog feature support in synthesizer. Logic optimization and performance improvement in synthesizer. Position Requirement: This position requires a Bachelor or Master's degree in EE/CS/CE with 3-5 years of industry experience. Candidate should be proficient with C/C++, Operating system concepts. Design modeling using Verilog/SV, VHDL or SysC. Knowledge and experience in RTL modeling of BFMs along with exposure to verification methodologies using UVM and SC/TLM is preferable. EDA/CAD tool development experience or logic design verification experience is highly preferred. Knowledge and experience in AI tools like Copilot or Claude code is preferred. Requires good communication skills, attention to details, and ability to work in multi-site/multi-person project. We’re doing work that matters. Help us solve what others can’t.
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Listed on workday · posted 2026-10-12. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.