Lead Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Design Engineer Location: Nanjing, China Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success. • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary: Senior Frontend Design Engineer for Advanced Physical IP Development. Join a growing and dynamic organization developing and leading the proliferation of best-in-class physical IP for industry-standard protocols. This is a tremendous opportunity to work with an experienced and full skillset team focusing on high-performance IP AND to engage with technology sector’s top companies making an impact in our world. The role will be a highly motivated technical expert who is able to work independently and collaboratively complete IP projects within required timelines and deliverables with high quality. The candidate will contribute to overall specification definition, industry standard workgroup, digital architecture, digital RTL, low power design, etc., as well as partnering with Project Manager collaborating with digital verification, analog, layout, backend design, lab validation teams in Nanjing and multiple worldwide geographies, and pre/post-silicon application support for global customers. The candidate should possess strong communication skills in both English and Mandarin with ability to manage multiple tasks and priorities on day-to-day basis. Primary Responsibilities: Key contributor and senior technical engineer in the IP frontend design team, especially on high-performance Consumer PHYs including eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA, etc. Drive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process Understanding of synthesis, constraint generation, power management and DFT Understanding of low-power designs and features (power islands, state retention, isolation, etc.) Work with digital verification team to specify coverage points, testing strategy, corner conditions, stimulus creation and FPGA/Palladium testing Partner closely with Project Management Office to collaborate with various skill groups in Nanjing and multiple worldwide geographies to complete the IP deliverables with high quality, including Analog, Layout, Backend, Firmware, Lab Bring-up/Validation, Pre/Post-Silicon Product Engineering Work with wider engineering and IP delivery/release teams to develop and use infrastructure to integrate IPs into subsystems and QA for customer releases Position Requirements: MS / BS in Electrical/Computer Engineering or related degree. 5+ years of relative industry working experience. 3+ years of experience in ASIC design role for delivering advanced IP and/or ASIC/SOC products. Deep knowledge of best practices and flows in Design Architecture, RTL design/verification and ASIC end-to-end methodology. Knowledge of one or more industry serial standards, such as USB, DP, PCIe, Ethernet, etc. Understanding basics of Analog Mixed-Signal, SI/PI, Post-Silicon Validation, and system view of physical interface IPs and their typical applications. One Team mentality with a passion to innovate and can-do attitude. Strong cross-functional communication skills in both English and Mandarin. Self-starter and highly motivated. Qualifications as Plus Direct experience of high-speed serial interface link IPs in advanced technology nodes. Knowledge of multiple programming languages, System Verilog, Python, C/C++, etc. Knowledge of embedded microcontroller or DSP usage and FW. Experience with various Cadence ASIC design tools. We’re doing work that matters. Help us solve what others can’t.