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GPU Physical Design Engineer Intern

Intel

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What physical roles keep asking for: Python (21%), Perl (14%) — counted across their open postings here.

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Interviews for physical roles keep coming back to Python, Perl. Practise those questions before you sit with Intel.

Questions you are likely to be asked

  1. Why do you want to join Intel?
  2. What is your experience with Perl? Tell me one thing you learned the hard way.
  3. How would you design an API for a feature you have worked on?
  4. What do you do when a production issue happens on your code?
  5. Walk me through a system you built. How was it designed, and what would you change now?

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Job Details: Job Description: As a Physical Design Engineering Undergraduate Intern, you will play a key role in supporting the development of cutting-edge semiconductor solutions. You will contribute to the creation, optimization, and verification of physical design and layout for high-performance systems-on-chip (SoCs). Your work will help ensure efficient designs that meet power, performance, and area targets, making a tangible impact on Intel's product roadmap and technological advancements. Business group You will be part of Intel's Data Center Group (DCG), which focuses on designing and delivering innovative solutions to meet the growing demands of data-centric computing. DCG drives improvements in cloud computing, AI, and edge innovations, supporting Intel's mission to enable a smarter, connected world. The primary responsibilities for this role will include, but are not limited to: Assist in physical design implementation, including placement, routing, and optimization of high-performance SoC designs. Perform design rule checks (DRC) and layout versus schematic (LVS) validations to ensure design integrity. Collaborate with cross-functional teams to analyze and resolve design challenges related to timing, power, and area. Contribute to the development and enhancement of design methodologies and automation tools. Support hardware engineering teams in validating and debugging design features through simulation and analysis. Qualifications: Minimum Qualifications : Minimum qualifications are required to be initially considered for this position. Pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 0-1 years of hands-on experience in physical design engineering with demonstrated skills gained through internships, academic projects, coursework, or hands-on training. Advanced experience in EDA tools for physical design, such as Cadence, Synopsys, or similar platforms. Knowledge of semiconductor design principles, including timing, power optimization, and layout techniques. Intermediate to Advanced English proficiency (both verbal and written). Must have unrestricted - permanent right to work in Costa Rica. Preferred Qualifications: Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Familiarity with scripting languages, such as Python or Perl, for design automation. Strong analytical and problem-solving skills combined with the ability to work effectively in a collaborative team environment. Passion for advancing technology and contributing to innovative design solutions. We invite you to bring your curiosity, creativity, and drive to Intel as we work together on technologies that shape the future of computing. Job Type: Student / Intern Shift: Shift 1 (Costa Rica) Primary Location: Costa Rica, San Jose Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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Listed on workday · posted 2026-10-01. ApplySarthi collects openings and links to application pages; the role is advertised by Intel, not by us.