ASIC DFT Engineer
Broadcom
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This role on the market
309 open asic roles across 18 companies are on ApplySarthi right now, most of them in Bengaluru (41), Hyderabad (19), Pune (3).
- Principal ASIC Design EngineerNokia
- ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal)Boeing
- ASIC Design Engineer, GPU Core Pipeline IPNvidia · bengaluru
- SoC/ASIC ArchitectAstspacemobile
- ASIC Reliability Analysis EngineerMicron
What asic roles keep asking for: Python (55%), Perl (34%), C++ (24%) — counted across their open postings here.
Broadcom has 435 open roles listed here.
- UK&I Security CTO
- Finance Analyst
- Finance Analyst
- SerDes Applications Engineer
- SerDes Applications Program Manager
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for asic roles keep coming back to Python, Perl, C++. Practise those questions before you sit with Broadcom.
Questions you are likely to be asked
- Why do you want to join Broadcom?
- What is your experience with C++? Tell me one thing you learned the hard way.
- What do you do when a production issue happens on your code?
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
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Practise the ASIC DFT Engineer at Broadcom interview free →Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: DFT Engineer for ASIC/Chip level ATPG Broadcom's ASIC Product Division is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will lead DFT programs from chip-level specification through implementation, verification, and product release to production. The candidate will participate in all phases of SoC DFT activities for Broadcom APD (ASIC Products Division) designs, including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post-silicon debug, and yield improvement to meet product test metrics. Responsibilities also include collaborating with physical design and STA teams for DFT-mode timing closure and directly interfacing with external customers. Responsibilities: Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC. Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration. Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns. Collaborate closely with STA and design integration engineers for timing and design closure. Generate, verify, and debug test vectors prior to tapeout release. Validate and debug test vectors on ATE during silicon bring-up. Assist with silicon failure analysis, diagnostics, and yield improvement efforts. Interface with customers, physical design teams, and global test engineering/manufacturing teams. Work closely with IP DFT engineers and cross-functional stakeholders. Debug customer-returned parts (RMA) on ATE. Proficiency in scripting and automation (such as Python, TCL, or C++), with an emphasis on applying AI-augmented development to streamline test flows. Develop innovative DFT solutions for advanced process nodes (3nm and beyond). Automate DFT and test vector generation flows. Skills/Experience: Strong DFT architecture and implementation background (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6) Proficiency with EDA tools for scan insertion, compression, and ATPG (e.g., DFT Compiler, TestKompress, TetraMax, FastScan) Hands-on experience with memory and logic BIST strategies, verification, and debug across embedded memories (SRAM, CAM, eDRAM, ROM) Experience with In-Field testing solutions a plus Extensive experience in Verilog coding, testbench development, ATPG pattern generation, simulation, and timing constraints/Test-STA Solid foundation in digital/analog circuit design, device physics, silicon manufacturing, synthesis, and transistor reliability Strong problem-solving, root-cause debug, statistical process control, and data analysis skills for silicon yield and quality improvement Effective cross-functional communication and project management skills to collaborate across physical design, test engineering, and operations Experience with ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN) is a plus Education & Experience: Bachelors in Electrical/Electronic/Computer Engineering and 8+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 6+ years of relevant industry experience Compensation and Benefits The annual base salary range for this position is USD 109,700.00 To USD 175,500.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Listed on workday · posted 2026-11-11. ApplySarthi collects openings and links to application pages; the role is advertised by Broadcom, not by us.