Senior Director, Engineering

Accountabilities: Lead the architecture, circuit design, and physical implementation of embedded memory compilers, including SRAM, ROM, single- and dual-port register files, and dual-port RAM. Define key memory design elements, including bitcell selection, peripheral architecture, decoders, sense amplifiers, write drivers, I/O, self-timing, redundancy, repair strategies, and assist circuits. Drive optimization of minimum operating voltage (Vmin), leakage, performance, area, and yield across process, voltage, and temperature (PVT) corners, process variation, and aging conditions. Own the technical roadmap for the memory portfolio, including new compiler variants, process nodes, feature enhancements, and design methodology improvements. Establish design, verification, and signoff methodologies, leading design and layout reviews, SPICE/FastSPICE characterization, statistical and Monte Carlo analysis, BIST/repair, DFT, and physical verification. Lead silicon validation programs, including test chip development, testing, characterization, and reporting. Lead, mentor, and develop a team of memory design engineers across circuit design, layout, characterization, and compiler automation. Define team objectives, conduct technical reviews, establish career development paths, and promote engineering rigor and continuous improvement. Allocate engineering resources across product roadmaps, customer commitments, and silicon programs while managing schedules, dependencies, and technical risks. Act as the senior technical lead in presales engagements, presenting the memory portfolio, qualifying opportunities, and shaping competitive technical proposals. Translate customer SoC requirements, including frequency, voltage, density, power, port configuration, and operating modes, into compiler specifications and PPA commitments. Partner with sales, field application engineering, and product management teams on RFQs, technical evaluations, and competitive benchmarking. Lead technical workshops and detailed design discussions with customer architects and engineering teams, responding to technical questionnaires and audit-style reviews. Own PPA analysis across the memory portfolio, evaluating performance, active and leakage power, area, and yield at both instance and SoC levels. Maintain competitive benchmarks against foundry and third-party memory IP, identify performance gaps, and prioritize improvements. Conduct sensitivity and trade-off analyses to guide architecture decisions, including bitcell selection, mux ratios, banking, assist circuits, and operating voltage ranges. Develop customer-facing technical materials, including datasheets, application notes, and technical white papers. Serve as the primary technical contact for strategic customers throughout evaluation, integration, tapeout, and silicon validation. Lead integration debugging, technical reviews, silicon correlation discussions, and root-cause analysis of customer-reported issues. Coordinate issue resolution across design, characterization, CAD, and product teams, and represent the organization in foundry partner meetings and industry conferences when required. Requirements: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline. 10+ years of embedded memory design experience, including demonstrated production tapeouts of SRAM and at least two additional memory types among ROM, single-port register files, dual-port register files, and dual-port RAM. Deep expertise in bitcell-level circuit design, memory peripheral circuits, self-timed paths, sense amplifier design, and assist circuit techniques. Hands-on experience across multiple semiconductor process nodes, including FinFET and/or advanced sub-7nm technologies. Strong command of SPICE simulation, statistical and Monte Carlo analysis, Vmin and yield modeling, and reliability analysis covering BTI, HCI, and electromigration. Working knowledge of memory compiler architecture and automation, including instance generation and the production of views such as Liberty (.lib), LEF, GDS, Verilog, and CDL. Practical experience with DFT and scan tools such as Tessent or FastScan, power integrity signoff tools such as RedHawk or equivalents, and physical verification flows including DRC, LVS, and parasitic extraction. Familiarity with RTL/Verilog modeling of memory compilers, test chip definition, silicon correlation, and SDK or automation development for compiler view generation. Proven engineering leadership experience, either through direct management or a senior technical leadership role overseeing a team of at least six memory designers. Demonstrated success in customer-facing technical roles, including presales engagements, PPA negotiations, and integration support. Excellent written and verbal communication skills, with the ability to present complex technical concepts to engineers, architects, and executive stakeholders. Proficiency in scripting languages such as Python, TCL, or Perl, and experience working in Linux-based design environments. Experience using AI tools such as Claude, OpenAI, or Gemini to support technical and engineering workflows. Experience presenting at industry conferences or technical venues such as ISSCC, VLSI Symposium, or custom integrated circuits conferences, or contributing to memory IP standards. Direct experience working with foundry partners on PDKs, bitcell qualification, and reference flow alignment. Preferred Qualifications: Experience leading memory compiler programs at a semiconductor IP vendor, foundry, or large semiconductor company. Background in low-power memory design for mobile, IoT, automotive, or AI/ML accelerator applications. Experience with multi-port memory architectures beyond two ports, such as three-port or four-port register files, and specialty memories including TCAM and multi-bank arrays. Benefits: Opportunity to lead advanced embedded memory IP development and influence semiconductor design across multiple technology nodes. Potential eligibility for equity, bonuses, commission, or other forms of additional compensation, depending on the position offered. Comprehensive medical, financial, and other employee benefits. Compensation determined by role, level, geographic location, relevant experience, technical skills, education, and other job-related factors.