Staff Engineer, Design Verification Engineering

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X) . Employer: Analog Devices, Inc. Job Title: Staff Engineer, Design Verification Engineering Job Requisition: 1010.1197.6 / R262387 Job Location: Chandler, Arizona Job Type: Full Time Rate of Pay: $172,390 - $199,229 per year Duties: Define and verify interfaces, state machines, and controlling logic required to implement new products for Data Center, Energy, and Automotive applications. Develop directed and constrained random test cases in SystemVerilog. Architect, implement, and/or manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity. SystemVerilog Assertion for Dynamic and Formal Verification. Design and maintain mixed-signal simulation (Cadence AMS); write Verilog-AMS and Real Number Models. Product definition involvement. Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master’s degree in Electrical Engineering, Materials Engineering, Physics, or closely related technical discipline (willing to accept foreign education equivalent) and four (4) years of experience as a Design Verification Engineer or related occupation performing module level design performing with Verilog RTL and function verification. Alternatively, employer will accept a Bachelor’s degree in Electrical Engineering, Materials Engineering, Physics, or closely related technical discipline (willing to accept foreign education equivalent) and six (6) years of experience as a Design Verification Engineer or related occupation performing module level design performing with Verilog RTL and function verification. Must also possess the following (quantitative experience requirements not applicable to this section): Demonstrated Expertise (“DE”) with mixed signal IC verification techniques (SystemVerilog and UVM), verification test plan creation, coverage closure, test case and regression suite development. DE defining, designing, and verifying experience with custom state machines and control logic for use with analog and mixed signal circuits such as data converters, linear regulators, high speed serial interfaces, and microcontrollers. DE defining and implementing custom digital interfaces (I2C, SPI, and UART). DE with logic synthesis with timing and placement constraints, timing and power analysis, logic equivalence checking, design for test, scan insertion, and ATPG. DE with verification tools (Xcelium or VCS), and scripting languages (Perl, Python, and C) . Contact: Eligible for employee referral program. Apply online at https://www.analog.com/en/careers.html and Reference Position Number: R262387. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law . Job Req Type: Experienced Required Travel: No Shift Type: 1st Shift/Days