SRAM Memory Design
Sec
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This role on the market
136 open memory roles across 22 companies are on ApplySarthi right now, most of them in Bengaluru (23), Hyderabad (15).
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Counted across 14 company job boards, updated as roles open and close.
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136 open memory roles are hiring right now across 22 companies, mostly in Bengaluru — so the questions repeat. Practise them before you sit with Sec.
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- Why do you want to join Sec?
- How do you test a design with users before it is built?
- How do you work with developers so the build matches the design?
- How do you balance what users ask for with what the business needs?
- Walk me through a design from your portfolio, from the problem to the result.
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Practise the SRAM Memory Design at Sec interview free →Position Summary Position: SRAM Memory Design Engineer: Roles and Responsibilities: • Design highly competitive circuits to meet performance/power specifications requested by customers • Guide and lead a group of engineers to deliver the SRAM IP in the given timelines • Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design. • Own the responsibility from SPEC to GDS and DK delivery. • Review circuits, robustness reports and identify potential robustness issues. • Review Layouts and suggest improvement areas to achieve competitive PPA • Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC • Must be able to communicate effectively across different teams. Role and Responsibilities Skills & Experience: • Master/Bachelor in electronics • Working experience in preferably Memory design • Understanding of RC network and FINFET fundamentals are necessary. • Custom or Compiler SRAM/ROM development experience • Fundamentals of process variability and its effect on memory design • Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM) • Strong understanding of circuit design fundamentals • Critical path modelling concept, various type of models ( RC, C, Pai,ladder) • Good knowledge of semiconductor physics. Like knowledge of finfet function, parasitic etc • Analysing layout and understanding of LLE effects. Skills and Qualifications Experience – 4 to 10 Years of experience Qualifications: B.Tech/B.E/M.Tech/M.E Disclaimer: Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here .
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Listed on workday · posted 2026-08-28. ApplySarthi collects openings and links to application pages; the role is advertised by Sec, not by us.