SOC Physical Design and STA Methodology Engineer

Position Summary About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Role and Responsibilities Roles and Responsibilities Experience in SoC Physical Design with proven track record in **flow and methodology development** (not just block implementation) Expert in scripting for EDA automation: **Python** (preferred), Tcl, Perl, UNIX shell Deep hands-on experience with PnR and Signoff tools: Synopsys (Fusion Compiler, PrimeTime, ICV, Formality) and/or Cadence (Innovus, Genus, Voltus, Tempus) Developed production-grade PnR flows for partition and Chip Top level designs including power planning, placement, optimization, and routing Strong STA fundamentals: Constraints (SDC) development, timing debug, OCV/POCV derates, PVT corners, and ECO flows Experience in low power and multi-voltage designs: UPF, power gating, voltage islands Built automation utilities for PnR execution, signoff analysis, and ECO implementation Solid understanding of libraries, cell architectures, and technology files for optimization and ECO stages. Experience with AI-driven optimization tools (DSO.ai, Cerebrus) Advanced ECO tool expertise (Tweaker, PrimeClosure) Formal verification (LEC) methodology experience Hierarchical STA and chip-top integration experience DTCO and advanced node (3nm, 2nm) exposure Debug, enhance, and release PnR and STA signoff flows for multiple projects and process nodes Develop utilities and automation to improve PPA, runtime, and ease of use for design teams Support partition and full-chip design teams on complex convergence issues, timing closure, and DRC fixing Explore and deploy new EDA capabilities and PPA optimization recipes to production flows Document flows, create regression tests, and train design teams on methodology best practices Skills and Qualifications Experience – 5 to 8 Years Qualifications B.Tech/B.E/M.Tech/M.E Disclaimer Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law. * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here .