Senior SOC Design Engineer

Job Details: Job Description: The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in the integration and pre-silicon validation of multiple IPs within Intel's client chipsets and SoC products. You will actively contribute to the development of cutting-edge microarchitecture, RTL logic design, and verification environments, ensuring the functionality and performance of next-generation features. Through collaboration with cross-functional teams, your work will drive innovation and establish quality improvements that impact Intel's product roadmap. Business group The IP Security Client Product Group focuses on delivering IPs, chipsets, and SoCs for Intel's client and server roadmap. As part of Intel Corporation's broader goals, the group empowers its members to innovate, grow, and deliver high-quality solutions that enhance Intel's leadership in the semiconductor industry. This team specializes in enabling end-to-end integration and pre-silicon validation to support Intel's cutting-edge technologies and products. Key Responsibilities Design and integrate microarchitecture, RTL logic, and verification environments across multiple IPs. Debug and validate features, ensuring functionality and performance alignment to design specifications. Develop robust test plans, coverage points, and test content for new architectural features. Collaborate with cross-functional teams, including IP Design, Firmware, Structural Design, DFX, emulation, and validation teams, to optimize platform architecture and design. Enhance organizational capabilities through contributions to quality and efficiency improvements and innovative methodologies. Lead initiatives to influence design or validation microarchitecture across the SoC Front End Design team. Qualifications: Minimum Qualifications Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. 6+ years of experience in RTL integration, validation techniques, and debug methodologies. Proficiency in industry-standard methodologies such as UVM and formal verification. Demonstrated expertise in microarchitecture design and integration. Technical ability to validate and debug complex IP interfaces, including Fabric, Platform Essentials, and IOs. Preferred Qualifications Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. Proven track record of leadership by example and guiding technical initiatives. Strong communication and collaboration skills with stakeholders across teams and locations. Ability to identify opportunities for efficiency improvement while maintaining high-quality standards. Passion for solving complex problems and proposing data-driven solutions. Take the next step in your career by joining a team that drives innovation, fosters growth, and develops groundbreaking technologies. Job Type: Experienced Hire Shift: Shift 1 (Malaysia) Primary Location: Malaysia, Penang Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.