Senior Principal Software Engineer
Cadence
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Questions you are likely to be asked
- Why do you want to join Cadence?
- What is your experience with C++? Tell me one thing you learned the hard way.
- How would you design an API for a feature you have worked on?
- What do you do when a production issue happens on your code?
- Walk me through a system you built. How was it designed, and what would you change now?
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Practise the Senior Principal Software Engineer at Cadence interview free →At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join the team behind Xcelium , the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning. We are looking for an experienced C/C++ software engineer to join the Xcelium Software Development Team to develop and enhance RTL/logic simulation products. Responsibilities: Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features. Enhance and support Timing Constraints Verification technology used inside Xcelium simulator. The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi‑billion‑node graphs. Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint. Collaborate with global team members to deliver high-quality results in a distributed environment. Write Specifications and Unit Tests for your code. Position Requirements/Qualifications: MS/PhD in Computer Science or Electrical Engineering. MS in Computer Science or Electrical Engineering with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience 5+ years of experience in EDA software development. Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool. Excellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog. Experience in multi-threaded/ concurrent programming. Ability to quickly learn new technologies and adapt to project requirements. Prior experience with RTL/logic simulation software development is an added plus. The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.
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Listed on workday · posted 2026-10-13. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.