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RTL-to-GDS implementation, Senior Principal Solutions Engineer

Cadence

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Questions you are likely to be asked

  1. Why do you want to join Cadence?
  2. Walk me through a system you built. How was it designed, and what would you change now?
  3. Tell me about a hard bug you tracked down. How did you find the cause?
  4. How do you decide what to test, and what does good code review look like to you?
  5. Describe a time a deadline forced a trade-off in quality. What did you choose and why?

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer Customers achieve superior performance for their Design PPA Goals. AE's are expected to possess Synthesis (logical and physical), Place and Route (primary focus) , STA / SDC skills and some experience supporting tapeouts. Experience with multivoltage design implementation and clock tree debugging is desirable. In addition, Solutions Engineers are expected to be able to articulate design methodologies involving Cadence tools and be 'elevator talk' proficient in the full Cadence tool portfolio. Development time will be spent gaining expertise in additional, or specialization tools, broadening focus from product emphasis to methodology, Full Flow Implementation Training, and learning to leverage success . Full Flow Services Projects involves owning block implementation, top level implementation and Signoff focused efforts. Job exposure will be on RTL to GDSII delivery of projects. There's an opportunity to get involved in competitive benchmarking on complex blocks including CPUs, GPUs and DSP cores. These projects involve implementation in multiple technology nodes on standard foundry solutions. If you are looking to gain experience in methodology, product delivery, and working on cutting edge technology, this is the right role for you. Position Requirements: * 7+ years experience and a strong technical knowledge of company products. * Design experience should include ASIC design using industry-standard hardware description languages (Verilog) * Senior Level Applications Engineer position with Deep Cadence or Synopsys place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) experience and knowledge are required * Innovate with Low Power and Multi-Voltage Design Techniques working with leading edge Wireless and Mobile Customers * Senior level Design Engineer position supporting RTL-to-GDS implementation flows using Encounter Digitial Implementation Platform * Manage strategic customer evaluations/benchmarks on Cadence's front-end solutions to establish technology differentiation and assert Cadence competitive advantages. Multiplex several issues and set priorities and exploit new technologies are essential for success in the position We’re doing work that matters. Help us solve what others can’t.

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Listed on workday · posted 2026-10-30. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.