ApplySarthiPrincipal Design Engineer
Cadence
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This role on the market
3,289 open design roles across 297 companies are on ApplySarthi right now, most of them in Bengaluru (289), Hyderabad (115), Delhi NCR (49).
- Senior Chip Design Verification EngineerNvidia
- Principal Digital Design Engineer - MCUNxp
- Structure Design EngineerCat
- RF IC Design and System Simulation EngineerBroadcom
- DRAM Principal Design Verification EngineerMicron
What design roles keep asking for: Python (19%) — counted across their open postings here.
Design Engineer jobs in Bengaluru · Design Engineer jobs in India · Remote Design Engineer jobs
Cadence has 666 open roles listed here.
- Application Engineer - Physical Design (Back-End)
- Senior Principal Design Engineer-Palladium & Protium Customer Enablement & Solutions
- Intern : SRAM development and methodologies
- IT -Staff Systems Engineer
- Product Engineer IIbengaluru
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for design roles keep coming back to Python. Practise those questions before you sit with Cadence.
Questions you are likely to be asked
- Why do you want to join Cadence?
- How would you design an API for a feature you have worked on?
- What do you do when a production issue happens on your code?
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
Prep Sarthi gives you a free mock interview: an AI interviewer asks you questions like these out loud, from your own CV and this job, and shows your score and your weakest answer.
Practise the Principal Design Engineer at Cadence interview free →At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Job role: Analog Circuit Design Exp: 8+ years Equivalent or Relevant Education: BE/ B Tech/ ME/ M Tech / MS or Equivalent or Relavent · In-depth understanding of high-speed Serdes/Memory interface circuits like I/O’s,PLL’s, Clocking, Datapath’s. · Hands on experience on PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits. · Strong Analog Design and I/O Design fundamentals. Knowledge of ESD/Reliability/SI/PI. · Must have excellent written and verbal communication skills as well as good problem-solving skills. · Prior experience of working on cutting edge technology nodes like 16nm/10nm/12nm/7nm is added advantage. We’re doing work that matters. Help us solve what others can’t.
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Listed on workday · posted 2026-10-26. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.