Physical Design Engineer
Broadcom
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This role on the market
412 open physical roles across 53 companies are on ApplySarthi right now, most of them in Bengaluru (23), Pune (6), Hyderabad (5).
- Senior Solutions Architect, Higher Education and Research, Multimodal and Physical AINvidia
- Physical AI Lab Manager & Manufacturing Tech Lead, Industry Specialist & Solutions, Auto & ManufacturingAmazon Web Services
- Sr. Staff Engineer, Physical DesignMarvell
- Corporate Physical Security Console Operator (Monday to Friday 12 pm. to 8 pm)Broadridge
- Senior CAD Engineer – Physical VerificationMicron
What physical roles keep asking for: Python (38%), Perl (22%) — counted across their open postings here.
Physical Design Engineer jobs in the United States · Python jobs · Ruby jobs · Shell scripting jobs
Broadcom has 372 open roles listed here.
- Analog Mixed Signal Design Engineer
- Principal Physical Design Engineer, STA
- Physical Design Engineer
- Principal Physical Design Engineer
- Physical Design Engineer
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for physical roles keep coming back to Python, Perl. Practise those questions before you sit with Broadcom.
Questions you are likely to be asked
- Why do you want to join Broadcom?
- What is your experience with Python? Tell me one thing you learned the hard way.
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
- How would you design an API for a feature you have worked on?
- What do you do when a production issue happens on your code?
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Practise the Physical Design Engineer at Broadcom interview free →Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Physical Design Engineer (New College Grad) — ASIC Products Division (APD) Location: San Jose, CA Position Type: Full-Time Who We Are — Physical Design Team in APD Broadcom’s ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the world’s most innovative technology companies—spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders—to co-design and manufacture complex, custom ASICs that power the modern digital backbone. The Physical Design team within APD is the world-class execution engine behind the industry's most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise, advanced IP, cutting-edge physical design methodologies in 3nm/2nm/A14 nodes, and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth challenges.We transform ultra-complex architectures into fully realized, high-yielding, first-pass silicon success. What Defines Our Physical Design Team Pioneering First-Pass Silicon in 3nm/2nm: Our team consistently pushes the boundary of physics, taking the largest and most complex die sizes from floorplan to tapeout on leading-edge foundry nodes (N7, N5, N3, and N2). Record-Breaking Scale & Complexity: We regularly execute full-chip physical implementation for ultra-large-scale ASICs exceeding tens of billions of transistors, multi-gigahertz clock frequencies, and dense multi-die 2.5D/3D integration (CoWoS, HBM3/4, chiplet architectures). Methodology & Flow Leadership: We develop and maintain cutting-edge in-house (AI Driven) automation and methodology across different EDA tools, setting the benchmark for signoff quality and turn-around-time (TAT). About the Role Broadcom’s ASIC Products Division (APD) is looking for a motivated Physical Design Engineer (NCG) to join our Physical Design team. In this role, you will work alongside experienced engineers in executing the implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. In this role, you will gain hands-on experience in complex block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across cutting-edge deep sub-micron nodes (N5/N3/N2/A14). Key Responsibilities Participate in block-level floorplanning, and run placement and route (P&R) flows using industry-standard EDA tools. Perform Static Timing Analysis (STA), debug timing paths, and execute ECOs for timing closure. Run Physical Verification checks (DRC, LVS, ERC, Antenna) and resolve signoff violations. Analyze IR drop and electromigration (EM) to ensure power grid integrity. Develop and maintain automated scripts (TCL, Python, Ruby) to enhance flow efficiency and productivity Basic Qualifications Education: Bachelor's Degree in Electrical Engineering, Computer Engineering + 2yrs of experience or Master’s degree in Electrical Engineering, Computer Engineering (Graduation date within the past 12 months). Solid understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals. Familiarity with static timing analysis (STA) concepts, clocking, and setup/hold timing. Hands-on coursework, lab experience, or academic projects using EDA design tools (Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, or Siemens tools). Proficient in scripting languages such as TCL, Python, Ruby, or Bash . Preferred Qualifications Prior internship or research experience in ASIC physical design, synthesis, or physical verification. Basic understanding of Design for Testability (DFT), low-power intent (UPF/CPF), and FinFET technologies. Excellent problem-solving, debugging, and analytical skills. Work Authorization / Eligibility Requirements Legal authorization to work in the U.S. is required Compensation and Benefits The annual base salary range for this position is USD 82,500.00 To USD 132,000.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Listed on workday · posted 2026-10-30. ApplySarthi collects openings and links to application pages; the role is advertised by Broadcom, not by us.