Mixed-Signal, Sr Principal Design Engineer
Cadence
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This role on the market
164 open signal roles across 34 companies are on ApplySarthi right now, most of them in Bengaluru (9), Hyderabad (2).
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What signal roles keep asking for: Python (17%), MATLAB (14%), C++ (12%) — counted across their open postings here.
Cadence has 598 open roles listed here.
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Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for signal roles keep coming back to Python, MATLAB, C++. Practise those questions before you sit with Cadence.
Questions you are likely to be asked
- Why do you want to join Cadence?
- What is your experience with MATLAB? Tell me one thing you learned the hard way.
- Tell me about a hard bug you tracked down. How did you find the cause?
- How do you decide what to test, and what does good code review look like to you?
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
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Practise the Mixed-Signal, Sr Principal Design Engineer at Cadence interview free →At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an opportunity to join a dynamic team of experienced engineers developing physical IP for industry-standard high-speed serial-links. The successful candidate will ideally be a highly-motivated self-starter who can work independently to complete assigned tasks and contribute to project leadership. The candidate will contribute to all mixed-signal design, verification, and testing aspects. This includes circuit design and development from a high-level architectural specification, post-silicon test plan development and execution, and collaboration with the digital team to achieve functional and performance closure. Candidate must have a thorough understanding of the following: Mixed-signal circuit design fundamentals Mixed-signal circuit design and verification flows Cadence analog design environment Basic signal processing concepts Familiarity with the following items is a plus: Serial link design techniques Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques MATLAB or C to facilitate architecture development Hardware description languages such as SystemVerilog or VerilogA for functional model development Scripting languages such as Perl or Python for automation Silicon validation testing knowledge and experience Other requirements: Excellent verbal and written communication skills Ph.D. EE degree with 5+ years or MS EE. degree with 7+ years of mixed signal design industry experience in advanced process technologies The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.
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Listed on workday · posted 2026-09-13. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.