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Lead Software Engineer - Low-Power Verification

Cadence

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What verification roles keep asking for: Python (49%), Perl (29%), C++ (23%), Linux (13%) — counted across their open postings here.

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  1. Why do you want to join Cadence?
  2. What is your experience with C++? Tell me one thing you learned the hard way.
  3. Describe a time a deadline forced a trade-off in quality. What did you choose and why?
  4. How would you design an API for a feature you have worked on?
  5. What do you do when a production issue happens on your code?

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms. As a Lead Software Engineer on the Palladium and Protium UPF R&D team you will be responsible for improving UPF compilation performance and correctness, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs. What you will do Contribute to the UPF compilation flow -- improve compilation performance, reduce instrumented capacity, and add self-checks across Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support. Rebuild UPF documentation around end-to-end compilation workflows, backed by valid SystemVerilog and UPF examples, and keep code and docs in sync through example-driven checks. Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state). Help consolidate and unify UPF compilation across Palladium and Protium. What we are looking for BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience. Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL). Ability to read, review, and reason about C++ code and object-oriented designs. Scripting experience in Perl, Tcl/Tk, and/or Python. Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output. Strong technical writing skills — able to author user guides, specifications, and workflow-first documentation. The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

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Listed on workday · posted 2026-10-13. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.