Lead Product Engineer: SoC Verification
Cadence
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This role on the market
719 open verification roles across 48 companies are on ApplySarthi right now, most of them in Bengaluru (154), Hyderabad (52), Pune (10).
- Verification EngineerPhilips
- SoC Verification Engineer - Design for Debug/Design For TestIntel · bengaluru
- Experienced ASIC-FPGA Verification EngineerBoeing · bengaluru
- Sr. SDM, Verification and Validation, Amazon Leo, D2D SoftwareAmazon
- Staff Pharmacist - Evernorth - Remote - Per Diem (Remote Order Verification)Cigna
What verification roles keep asking for: Python (49%), Perl (29%), C++ (23%), Linux (13%) — counted across their open postings here.
Cadence has 709 open roles listed here.
- Account Executive (Physical Systems Simulation)
- Principal Design Engineer
- Sr Design Engineering Group Directordelhi ncr
- Intern - Product Validation
- Principal Product Validation Engineerdelhi ncr
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for verification roles keep coming back to Python, Perl, C++, Linux. Practise those questions before you sit with Cadence.
Questions you are likely to be asked
- Why do you want to join Cadence?
- What is your experience with C++? Tell me one thing you learned the hard way.
- What do you do when a production issue happens on your code?
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
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Practise the Lead Product Engineer: SoC Verification at Cadence interview free →At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems Inc. is looking for a motivated Lead Product Engineer: SoC Verification to work with us in Belo Horizonte, Brazil for Perspec Team. Perspec is Cadence’s Portable Stimulus solution used by leading semiconductor companies to solve complex SoC and system-level verification challenges . This role sits at the intersection of verification methodology, system architecture, and EDA product engineering . You will work directly with advanced verification teams at major semiconductor companies to deploy Portable Stimulus (PSS) in real production environments and help drive the evolution of Perspec. The work spans formal languages , simulation, emulation, virtual platforms, firmware-driven verification, and post-silicon reuse , and increasingly involves AI-assisted verification workflows . Portable Stimulus is changing how system-level verification is done. In this role you will work on real verification problems at scale , interacting with some of the most advanced verification teams in the industry and helping shape how hardware/software co-verification is done across simulation, emulation, and silicon. If you enjoy deep technical problem solving, modeling complex systems, and working close to both customers and EDA tool development , this is a unique role. Cadence has been nominated as a Great Place to Work globally and in Brazil , and is also a Fortune 100 Best Companies to Work For . Job Description: Work directly with semiconductor design and verification teams to deploy Portable Stimulus methodologies in complex SoC programs. Help debug difficult generation and solver issues involving constraints, resources, execution ordering, and scenario realization . Investigate real-world modeling challenges that arise in large system-level PSS environments . Collaborate closely with Cadence R&D to diagnose tool issues, influence new features, and improve PSS standard Help define and refine methodologies for scalable system-level verification . Develop reference models, internal knowledge, and best practices used by both customers and Cadence field teams. Support advanced system-level verification use cases including: software-driven verification device programming flows reuse between simulation, emulation, and post-silicon integration with virtual platforms and firmware environments Contribute to emerging AI-assisted verification flows built around PSS models. Requirements: Complete Bachelor's degree in Computer Science or related areas. Experience in SoC verification, validation, or verification methodology Strong hands-on experience with SystemVerilog and UVM or embedded / bare metal environments Solid understanding of constrained-random verification and system-level test generation Experience debugging complex verification environments Strong programming or scripting skills (C/C++/Python or similar) Ability to work directly with engineering teams to solve difficult technical problems Nice to Have: Exposure to Portable Stimulus (PSS) or interest in learning it Experience with Perspec or other PSS tools Experience working with complex SoC subsystems and protocols such as PCIe, DDR, networking , or ARM-based SoCs Experience with embedded software programming and bare-metal environments Familiarity with emulation, virtual platforms, or post-silicon validation Experience developing verification methodology or reusable verification libraries Additional Job Details: Employment category: CLT. Employment term: 40 hours/week. Competitive benefits. Location: Av Contorno 5800, Belo Horizonte, Minas Gerais, Brazil. Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com We’re doing work that matters. Help us solve what others can’t.
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Listed on workday · posted 2026-10-14. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.