ApplySarthi

Lead Design Engineer

Cadence

Tailor my CV for this job, freeView job and applyYour CV rewritten for this role, from your real experience. Sign in with Google, nothing to install.

Got this interview? Our apps help you get the job.

Prep SarthiFree 7-min demoPractise this interview with an AI interviewer, out loud.Unlimited mocks · ₹99/month →Live Sarthi30 min free demoAnswer hints during the real call, hidden from supported screen sharing.Unlimited interviews · ₹99/2 days · Windows →

This role on the market

2,950 open design roles across 255 companies are on ApplySarthi right now, most of them in Bengaluru (279), Hyderabad (99), Delhi NCR (52).

What design roles keep asking for: Python (16%) — counted across their open postings here.

Design Engineer jobs in Bengaluru · Design Engineer jobs in India

Cadence has 604 open roles listed here.

Counted across 14 company job boards, updated as roles open and close.

Preparing for this interview

Interviews for design roles keep coming back to Python. Practise those questions before you sit with Cadence.

Questions you are likely to be asked

  1. Why do you want to join Cadence?
  2. How would you design an API for a feature you have worked on?
  3. What do you do when a production issue happens on your code?
  4. Walk me through a system you built. How was it designed, and what would you change now?
  5. Tell me about a hard bug you tracked down. How did you find the cause?

Prep Sarthi gives you a free mock interview: an AI interviewer asks you questions like these out loud, from your own CV and this job, and shows your score and your weakest answer.

Practise the Lead Design Engineer at Cadence interview free →

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design verification of ASICs for Palladium. Position is based in Bangalore Will have to work at IP, Sub-System and SOC level verification. Test plan creation, functional coverage plan and coding of functional coverage bins. Will be involved in post silicon validation/bring up. Job Requirements: Strong expertise in Verilog, HVL( SV/Specman e) with UVM/OVM/eRM methodology. Experience in functional coverage/code coverage/assertions development and closure. Experience in test plan creation. Exposure to PCIe and LPDDR verification. Strong debug skills Should be process oriented and have a passion for scripting/automation. Should be a good team player Effective cross-team communication and documentation skill is strongly preferred. Minimal qualification requires BS/MS degree ECE or CS with 4+ years of experience in related fields. We’re doing work that matters. Help us solve what others can’t.

Match this job to your CV

ApplySarthi scores your CV against this role, shows the skills you are missing, and writes a tailored version for the application.

Check my match →

Similar open roles

Need answers during your interview? Try Live Sarthi.

Live Sarthi, an Interview Sarthi app, shows answer suggestions during the call.

Try Live Sarthi free →

A Windows app, from the same team as ApplySarthi.

Listed on workday · posted 2026-09-06. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.