DFT Engineer
Broadcom
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This role on the market
135 open dft roles across 16 companies are on ApplySarthi right now, most of them in Bengaluru (26), Pune (4), Hyderabad (3).
- Design-for-Test (DFT) Engineer — ASIC Backend – (Associate, Experienced, or Lead)Boeing
- Design / DFT Director (NVE Engineering)Micron
- DFT ATPG EngineerNvidia
- Sr DFT EngineerNxp · hyderabad
- Senior Principal Engineer-DFTMarvell
What dft roles keep asking for: Perl (54%), Python (51%), C++ (18%) — counted across their open postings here.
Dft Engineer jobs in Bengaluru · Dft Engineer jobs in India · Perl jobs
Broadcom has 408 open roles listed here.
- Senior Custom ASIC Engineering Lead
- Senior/Staff Process Integration Engineer (Optoelectronics)
- Staff Engineerbengaluru
- Memory Layout Design Engineerbengaluru
- Memory Layout Design Engineerbengaluru
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
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Questions you are likely to be asked
- Why do you want to join Broadcom?
- What is your experience with Perl? Tell me one thing you learned the hard way.
- Tell me about a hard bug you tracked down. How did you find the cause?
- How do you decide what to test, and what does good code review look like to you?
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
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Practise the DFT Engineer at Broadcom interview free →Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis. Key Responsibilities : Work closely with the ATE engineer on yield improvement and analysis. Develop ATE patterns, manage the hand-off process, and perform silicon debugging. Participate in block and chip-level DFT implementation, developing and executing all related tasks. Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools. Perform ATPG and pattern simulation for both MBIST and scan. Collaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up. Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology. Required Qualifications: Bachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of related experience Required experience in silicon bring-up and yield improvement. Solid understanding of DFT techniques. Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process. Experience in MBIST architecture and insertion. Experience in analyzing and debugging simulation failures. Solid understanding of digital logic fundamentals. Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite. Proficiency with Perl or other scripting languages. Strong communication and interpersonal skills. Plus: Experience in STA constraint development in DFT modes Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Listed on workday · posted 2026-10-28. ApplySarthi collects openings and links to application pages; the role is advertised by Broadcom, not by us.