CPU Circuit Design Engineer
Intel
Tailor my CV for this job, freeView job and applyYour CV rewritten for this role, from your real experience. Sign in with Google, nothing to install.
Got this interview? Our apps help you get the job.
This role on the market
123 open circuit roles across 21 companies are on ApplySarthi right now, most of them in Bengaluru (18), Hyderabad (12), Chennai (2).
- Manager, Silicon Circuit and Power Integrity - Silicon Co-Design GroupNvidia
- Senior Optical Systems Validation Engineer - Optical Circuit Switch (OCS)PsiQuantum
- Digital Electronics Circuit & Unit Hardware Design Engineer (Lead or Senior)Boeing
- Senior/Principal Analog IC Circuit Design EngineerNxp
- Staff Memory Circuit Design EngineerBroadcom · bengaluru
What circuit roles keep asking for: Python (32%), Perl (19%), Deep learning (12%) — counted across their open postings here.
Intel has 954 open roles listed here.
- Partner Marketing Manager
- Silicon Packaging Architectbengaluru
- Electrical Validation Engineer (Temporary position)
- Device Engineer
- Intern System Software Development Engineer
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for circuit roles keep coming back to Python, Perl, Deep learning. Practise those questions before you sit with Intel.
Questions you are likely to be asked
- Why do you want to join Intel?
- Tell me about a hard bug you tracked down. How did you find the cause?
- How do you decide what to test, and what does good code review look like to you?
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
- How would you design an API for a feature you have worked on?
Prep Sarthi gives you a free mock interview: an AI interviewer asks you questions like these out loud, from your own CV and this job, and shows your score and your weakest answer.
Practise the CPU Circuit Design Engineer at Intel interview free →Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful. Responsibilities: Drives performance verification (PV) methodology and circuit / timing quality signoff for the CPU team. Evaluates new process nodes through circuit simulations and/or block scaling methods, recommends frequency targets for the CPU with an early understanding of u-architectural growth. Makes informed trade-offs between performance, power, area, and effort. Works with design domains RTL/circuit/SD to converge to timing targets with no compromise on quality or schedule. In addition to pre-silicon responsibilities, this individual will grow to own pre-to-post silicon VF correlation and drive debug of circuit marginality sightings. Must demonstrate a track record of execution and design ownership in advanced process technologies. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences. Minimum Qualifications: Bachelors & 6+ years or Masters & 4+ years in Electrical & Computer Engineering, Computer Engineering, Electrical Engineering or related field. 5+ years of CPU circuit or backend design experience. 5+ years of experience in circuit design and STA. Preferred Qualifications: In-depth circuit design knowledge and ability to make PPA tradeoff decisions. In-depth STA knowledge and circuit quality signoff criteria for tape-in. Ability to guide debug of post-silicon circuit marginality sightings. Ability to handle incomplete, fuzzy task definitions and drive them to closure. Hands on individual contributor who can delegate when necessary to meet stringent schedules. Led technical teams of 2-3 engineers. Self-motivated, team player and easy to work with. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Match this job to your CV
ApplySarthi scores your CV against this role, shows the skills you are missing, and writes a tailored version for the application.
Check my match →Similar open roles
- CPU DFT ManagerIntel · bengaluru
- CPU Circuit Design LeadIntel · bengaluru
- IP RTL Senior Design EngineerIntel · bengaluru
- Senior Director , Data and IntelligenceIntel · bengaluru
- SoC Verification EngineerIntel · bengaluru
- PDK EngineerIntel · bengaluru
- PDK EngineerIntel · bengaluru
- CPU Physical Design EngineerIntel · bengaluru
Need answers during your interview? Try Live Sarthi.
Live Sarthi, an Interview Sarthi app, shows answer suggestions during the call.
- Hidden from supported screen sharingThe overlay stays out of supported Windows screen captures.
- Answers start in about 1.5 secondsResponse time varies with your connection and model.
- From your own CVYour projects and your experience, not a generic script.
- 30 minutes freeThen ₹149 for a 2-day pass with unlimited calls — you pay for the days you are interviewing, not a subscription.
A Windows app, from the same team as ApplySarthi.
Listed on workday · posted 2026-10-10. ApplySarthi collects openings and links to application pages; the role is advertised by Intel, not by us.