CMOS SerDes or High-speed I/O, Lead Analog IC Design Engineer
Cadence
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This role on the market
25 open serdes roles across 9 companies are on ApplySarthi right now.
- Staff Firmware/Software Engineer - Embedded SoC/Microcontroller/DSP/SERDES/AEC/MicroLED/ODSP/PHY/AI ConnectivityMarvell
- SerDes Application EngineerBroadcom
- Principal SerDes System/DSP Design EngineerCiena
- High Speed SerDes Validation Engineer - New College Grad 2026Nvidia
- Advanced R&D - SerDes Architect and Modeling EngineerKandou Ai
What serdes roles keep asking for: Python (36%), C++ (32%), Supply chain (16%), MATLAB (12%) — counted across their open postings here.
Cadence has 663 open roles listed here.
- Sr AE Manager - Adams
- Principal Application Engineer-Marc
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Counted across 14 company job boards, updated as roles open and close.
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Questions you are likely to be asked
- Why do you want to join Cadence?
- How would you design an API for a feature you have worked on?
- What do you do when a production issue happens on your code?
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
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Practise the CMOS SerDes or High-speed I/O, Lead Analog IC Design Engineer at Cadence interview free →At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role Overview The Lead Analog IC Design Engineer is responsible for designing and developing analog and mixed-signal circuits- from initial concept and specification through final verification- to ensure conformance with customer requirements. Required Qualifications • At least three years of experience designing and developing CMOS SerDes or high-speed I/O integrated circuits. • Design experience with most of the following SerDes circuit blocks: Transmitters and receivers, serializers and deserializers, phase interpolators, low-jitter PLLs, high-speed clock-distribution circuits, bias circuits, and voltage regulators. • Good understanding of jitter and signal-equalization techniques. • Proficiency with CAD tools for circuit simulation, layout, and physical verification. • Master’s degree or Ph.D. in electrical engineering. • Strong problem-solving skills and analog design aptitude. • Clear written and verbal communication skills. • Ability to collaborate effectively in a team environment. Preferred Qualifications • Working knowledge of common SerDes standards and their electrical requirements. • Experience with Cadence design tools and laboratory testing. • Design experience at data rates above 10 Gbps and in process technologies below 28 nm. The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.
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Listed on workday · posted 2026-10-22. ApplySarthi collects openings and links to application pages; the role is advertised by Cadence, not by us.