ASIC VERIFICATION ENGINEER
Broadcom
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This role on the market
534 open verification roles across 51 companies are on ApplySarthi right now, most of them in Bengaluru (112), Hyderabad (52), Pune (9).
- Staff System Engineer, Integration & VerificationJobgether
- Head of Formal Verification (m/f/d)Lubis Eda
- ASIC Design Verification Engineer, Amazon LeoAmazon Kuiper Manufacturing Enterprises LLC
- Verification EngineerIMC
- Hardware (PCBA) Design and Verification Intern (Winter 2027 - 4 months)Ciena
What verification roles keep asking for: Python (19%) — counted across their open postings here.
Broadcom has 373 open roles listed here.
- Senior z/OS Systems Programmer
- R&D Engineer Software 5
- Agentic AI Architect
- Instructional Designer - Mainframe Education
- Technical Lead / EPM
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for verification roles keep coming back to Python. Practise those questions before you sit with Broadcom.
Questions you are likely to be asked
- Why do you want to join Broadcom?
- What is your experience with Perl? Tell me one thing you learned the hard way.
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
- How would you design an API for a feature you have worked on?
- What do you do when a production issue happens on your code?
Prep Sarthi gives you a free mock interview: an AI interviewer asks you questions like these out loud, from your own CV and this job, and shows your score and your weakest answer.
Practise the ASIC VERIFICATION ENGINEER at Broadcom interview free →Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job Description What You can Expect - - Work on Latest cutting edge CSG Switches. - To be part of the team working on defining many Firsts for the AI Network Infrastructure Ecosystem. - Develop and maintain verification Environment in Mix of SV/UVM. - Understanding of the End to End spec along with Network & System topology. - Closely working with Arch/uArch/Design team for Test Plan development and closure of the feature set across Blocks/Top level. - Coverage Closures, Gate Level Simulations along with end to end verification cycle. What we are looking for - - Bachelor's/Masters/PhD with Verification experience of 8+ years - Wide exposure to chip level (SoC) verification and SystemVerilog/UVM methodology a MUST - Exposure to any one of the scripting languages - Perl or Python or SED/Awk - Expertise in Co-Simulations (HW/SW) Flow and debugs - Knowledge of networking protocols(L2/L3/L4, 1588TS, UEC) desired but not necessary. - Expertise in the High Speed bus protocols desired - PCIe, Ethernet, AXI4.0 - Exposure the Chip level Interconnect/Testability Functions - JTAG, I2C, PLLs etc - Experience in GLS, Coverage Driven Methodology, ATE - Good exposure in Simulation tool usage for simulation (VCS) and waveform debug(Verdi) and formal tools like Jasper. - Exposure to Test Bench Accelerators /Emulation Platforms. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Listed on workday · posted 2026-08-28. ApplySarthi collects openings and links to application pages; the role is advertised by Broadcom, not by us.