ASIC TOP Floorplan Intern, 2027
Nvidia
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This role on the market
7 open floorplan roles across 2 companies are on ApplySarthi right now, most of them in Bengaluru (1).
- ASIC Design - Floorplan EngineerBroadcom
What floorplan roles keep asking for: Perl (100%), Python (100%), C++ (86%), Linux (14%), Ruby (14%) — counted across their open postings here.
C++ jobs · Perl jobs · Python jobs
Nvidia has 3,820 open roles listed here.
- Software Developer - Networking
- Manager, Silicon Circuit and Power Integrity - Silicon Co-Design Group
- Senior Physical Design Methodology Engineerbengaluru
- Electro Optics Student
- Manager, Software Verification
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for floorplan roles keep coming back to Perl, Python, C++, Linux. Practise those questions before you sit with Nvidia.
Questions you are likely to be asked
- Why do you want to join Nvidia?
- What is your experience with C++? Tell me one thing you learned the hard way.
- What is a weakness you are working on, and how?
- Tell me about yourself, and why this role is the right next step.
- Tell me about a problem you solved at work that you are proud of.
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Practise the ASIC TOP Floorplan Intern, 2027 at Nvidia interview free →We are now looking for an Intern ASIC TOP Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you will be doing: Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development. Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities. Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions. You will build tools and improve existing infrastructure to optimize chip area and speed of execution. What we need to see: Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work/learning experience. Experience in Verilog, System Verilog or similar HVL. Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure. Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview. Python, Perl and C/C++ programming language experience. Ways to stand out from the crowd: Experience in driving development of large scale ASIC floorplan is a huge plus. NVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.
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Listed on workday · posted 2026-10-19. ApplySarthi collects openings and links to application pages; the role is advertised by Nvidia, not by us.