ASIC Processor Complex Engineering Co-op (January 2027 - 4 months)

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters. Our R&D headquarters in Ottawa is home to our world leading Digital Signal Processing (DSP) WaveLogic ASIC chipsets, forming the core of Ciena’s Optical Communications Systems. As a member of the team, this student will help develop and evolve the processor complex that will be used in our next generation ASIC devices. This role will include infrastructure, design and integration of Ciena’s intellectual property and offers hands-on opportunities across ASIC Design, verification and scripting. How you will make an impact: Work with a fast-paced team developing large-scale DSP ASICs for optical communications, with training and access to key engineers while working on these projects. Interact daily with other developers and team leads for guidance and support. Develop small design blocks and analyze designs for correctness and speed. Implement and verify designs. Write verification testbenches (SV/UVM) to prove the functionality of individual blocks. Develop and enhance Python scripts for simulation regression launching, reporting and analysis, build and debug workflow optimization, and a relational database application for debug and reporting. Code, build and test functions implemented in firmware and running on the processor complex. The must haves: Education: Actively enrolled in a degree program in electrical or computer engineering, Programming experience (ideally using at least one of C, Java, Python, TCL, and System Verilog). Familiarity with Linux based development environments. Nice to haves: Previous experience ASIC or FPGA development programs. Strong analytical and debugging skills. Familiarity with Agile JIRA, Confluence, GIT. Pay Range: The hourly pay range for this role is: $25.50 - 35.00 Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.