ASIC Physical Design Engineer
Broadcom
Broadcom is also hiring for this role in Singapore-Yishun.
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Skills named in this job
Read from the description itself, not inferred.
This role on the market
413 open physical roles across 60 companies are on ApplySarthi right now, most of them in Bengaluru (25), Pune (5), Hyderabad (5).
- Physical Failure Analysis (PFA) TechnicianMicron
- Senior Physical Design Methodology EngineerNvidia · bengaluru
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- Real Estate Physical Infrastructure SME ConsultantCapco
What physical roles keep asking for: Python (38%), Perl (19%) — counted across their open postings here.
Broadcom has 408 open roles listed here.
- Senior Custom ASIC Engineering Lead
- Senior/Staff Process Integration Engineer (Optoelectronics)
- Staff Engineerbengaluru
- Memory Layout Design Engineerbengaluru
- Memory Layout Design Engineerbengaluru
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for physical roles keep coming back to Python, Perl. Practise those questions before you sit with Broadcom.
Questions you are likely to be asked
- Why do you want to join Broadcom?
- What is your experience with Linux? Tell me one thing you learned the hard way.
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
- How would you design an API for a feature you have worked on?
- What do you do when a production issue happens on your code?
Prep Sarthi gives you a free mock interview: an AI interviewer asks you questions like these out loud, from your own CV and this job, and shows your score and your weakest answer.
Practise the ASIC Physical Design Engineer at Broadcom interview free →Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Skills and responsibilities: Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies. Able to handle a full RTL to GDS or Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis). In-depth knowledge of GPU/CPU/DSP architecture/algorithm and related physical design implementation techniques is highly advantageous. Proficiency in UNIX/Linux and scripting languages is advantageous. Required Qualifications: Degree, Masters or PhD in Electrical/Electronics/Computer engineering. Minimum of 5 years or more experience in a relevant field. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
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Listed on workday · posted 2026-11-02. ApplySarthi collects openings and links to application pages; the role is advertised by Broadcom, not by us.