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ASIC Engineer Intern

Ciena

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This role on the market

208 open asic roles across 19 companies are on ApplySarthi right now, most of them in Bengaluru (24), Hyderabad (6), Pune (2).

What asic roles keep asking for: Python (24%), Perl (13%) — counted across their open postings here.

Confluence jobs · Java jobs · Linux jobs · Python jobs

Ciena has 146 open roles listed here.

Counted across 14 company job boards, updated as roles open and close.

Preparing for this interview

Interviews for asic roles keep coming back to Python, Perl. Practise those questions before you sit with Ciena.

Questions you are likely to be asked

  1. Why do you want to join Ciena?
  2. What is your experience with Python? Tell me one thing you learned the hard way.
  3. Walk me through a system you built. How was it designed, and what would you change now?
  4. Tell me about a hard bug you tracked down. How did you find the cause?
  5. How do you decide what to test, and what does good code review look like to you?

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As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters. The Opportunity: Work term of 4 months extendable to 8, starting in January 2027. Ciena is seeking a student to contribute to the development and evolution of automation infrastructure used for next-generation ASIC devices. The role provides exposure to ASIC design, integration, layout, and verification activities within large-scale DSP ASIC development for optical communications. The position is aligned to a student’s experience, strengths, and technical interests. How you will make an impact: Contribute to the development of automation infrastructure for ASIC devices. Collaborate with developers and team leads to advance ASIC design, layout, integration, and verification activities. Develop design blocks and evaluate designs for correctness and performance. Implement netlists into silicon-realizable layouts and automate placement and extraction workflows. Create constraints, analyze implementation reports, and automate ASIC integration processes. Develop reusable SystemVerilog/UVM verification components. Enhance Python-based reporting, analysis, build, simulation, and debug workflows. The must haves: Programming experience using one or more of Java, Python, TCL, Skill/Ocean, or SystemVerilog. Familiarity with Linux-based development environments. Nice to haves: Previous experience with ASIC or FPGA development programs. Strong analytical and debugging skills. Familiarity with Agile, JIRA, Confluence, and Git. Pay Range: The hourly pay range for this position is $25.50 - $35.00. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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Listed on workday · posted 2026-09-22. ApplySarthi collects openings and links to application pages; the role is advertised by Ciena, not by us.