Silicon Engineer

About the role

Anthropic runs some of the largest AI training and inference workloads in the world, across multiple hardware platforms. We work from the chip level up with our silicon partners, and we are now deepening that investment by building a custom silicon team.

You will be one of a small number of people covering a large surface. We are opening searches across the key domains below, and we are interested in candidates whose center of gravity sits in any of them:

• Front-end design
• Pre-silicon verification
• Physical design
• Design for test
• Analog and mixed-signal
• Technology and foundry
• CAD and design infrastructure
• Packaging, signal integrity, and power integrity

This is a role for someone who has shipped silicon, has a realistic relationship with schedules, and is comfortable making consequential calls without a large organization behind them. 

Key responsibilities

• Take part in end to end activities for the program: strategy, specification, execution and the technical bar.
• Write the specifications and interface definitions that others design against and keep them coherent as the architecture converges
• Make and own directional calls: technology and IP selection, where we build versus buy versus license, and where we take design authority versus rely on partners
• Build and share AI-assisted approaches to the code-like parts of your domain, and help the team learn what Claude can genuinely accelerate
• Contribute to the architecture and micro-architecture discussion from your domain's perspective, including the tradeoffs your area imposes on the rest of the chip
• Partner with Anthropic's inference, performance, kernels, and infrastructure teams on hardware-software co-design, and with our hardware systems team on bring-up and integration
• Support first-silicon bring-up and debug when it arrives, regardless of which domain you came in through

Minimum qualifications

• Deep, hands-on expertise in at least one silicon domain: front-end design, pre-silicon verification, physical design, design for test, analog and mixed-signal, technology and foundry, design infrastructure, or packaging and signal/power integrity
• Direct personal contribution to silicon that taped out and shipped, with ownership you can speak to in detail
• Working fluency in the domains adjacent to your own, sufficient to reason about chip-level tradeoffs outside your specialty
• Experience working with external partners — ASIC houses, IP vendors, foundries, or test partners — including reviewing their work and holding a technical bar
• Track record of owning directional technical decisions and their consequences, not only making recommendations
• Practical experience using AI coding tools in your own work, and clear ideas about where they help and where they do not
• Clear written and verbal communication, and experience driving alignment across teams and organizations
• Comfort operating with high autonomy and little scaffolding on a highly dynamic program

Preferred qualifications

• Experience on machine learning accelerators, high-performance compute, or other large, high-bandwidth designs
• Experience on a founding or early-stage silicon team, including standing up flows, methodology, or tooling from nothing
• Experience with both partner-executed and fully in-house programs, and a view on the tradeoffs between them
• Familiarity with the chip-package-system interface and the tradeoffs that cross it
• Experience with hardware-software co-design and working directly with compiler, kernel, or runtime teams
• Experience building or extending AI-assisted design, verification, or physical design flows
• Depth in memory subsystems, on-die interconnect, numerics, or low-power design

Representative projects

• Writing the specification for a compute datapath and defending its numeric format strategy against the alternatives
• Standing up front-end flows and release management from scratch, then handing releases to an ASIC partner on a fixed cadence
• Running fast in-house place-and-route loops on a critical block and feeding PPA reality back into the architecture
• Selecting and qualifying PHY IP, then validating it on first silicon
• Building a formal verification methodology for a new block and deciding where formal earns its keep versus simulation
• Defining test strategy and the automated-test-equipment handoff interface with our partner
• Prototyping a Claude-assisted workflow for RTL review, coverage triage, or specification consistency checking, and reporting honestly on what it did and did not do
• Debugging a first-silicon failure that crosses your domain and someone else's