DFT Engineer CH, UK
Kandou Ai
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This role on the market
87 open dft roles across 14 companies are on ApplySarthi right now, most of them in Bengaluru (16), Pune (3), Hyderabad (3).
- Senior DFT EngineerNvidia
- Lead DFT EngineerNxp · delhi ncr
- Staff SOC DFT EngineerIntel
- Staff Engineer – DFT EngineeringAnalogdevices · bengaluru
What dft roles keep asking for: Python (18%), Perl (17%) — counted across their open postings here.
Kandou Ai has 16 open roles listed here.
- Advanced R&D - Physical Design Engineer
- Internship - AI Engineer
- Director of Silicon Characterization
- Advanced R&D - Internship - Digital Design
- Advanced R&D - Internship - Signal Processing
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for dft roles keep coming back to Python, Perl. Practise those questions before you sit with Kandou Ai.
Questions you are likely to be asked
- Why do you want to join Kandou Ai?
- How do you decide what to test, and what does good code review look like to you?
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
- How would you design an API for a feature you have worked on?
- What do you do when a production issue happens on your code?
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Practise the DFT Engineer CH, UK at Kandou Ai interview free →Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you. We are actively seeking a resourceful DFT Engineer based in Lausanne, Switzerland or UK Key Responsibilities : Hierarchical MBIST and scan insertion, BSD implementation ATPG pattern generation, coverage analysis, converging to high coverage metrics Pattern simulations with timing Defining test mode timing constraints, analyzing the timing reports and converge timing Developing cycle accurate functional patterns using IJTAG methodology Closely working with the test and production engineering teams to debug and bring up devices at probe and final test Debugging silicon issues Skills: Excellent communication skills, and strong team player with can do type of attitude Excellent debugging skills Good scripting skills to develop automation Qualifications : 5+ years of DFT experience including implementation, test pattern development, and simulation Proven experience in contributing to DFT solution to complex designs Experience working with IJTAG methodologies Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics Good debug capabilities in simulating patterns with timing Experience with industry standard EDA tools for DFT, timing, and simulation Knowledge of System Verilog Education: Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher) Find more English Speaking Jobs in Switzerland on Arbeitnow
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Check my match →Similar open roles
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Listed on arbeitnow · posted 2026-09-27. ApplySarthi collects openings and links to application pages; the role is advertised by Kandou Ai, not by us.