Analog Layout Engineer (Lead)
Kandou AI
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This role on the market
231 open analog roles across 19 companies are on ApplySarthi right now, most of them in Bengaluru (34), Hyderabad (9), Delhi NCR (7).
- Senior/Staff Engineer, Analog LayoutMarvell
- Staff Analog Mixed-Signal Design EngineerNokia
- Analog Design Flow and Infrastructure Design Automation ManagerIntel · bengaluru
- Principal/MTS, Analog Design EngineeringMicron
- Lead Analog Layout EngineerCiena
What analog roles keep asking for: Python (20%), MATLAB (15%) — counted across their open postings here.
Kandou AI has 2 open roles listed here.
Counted across 14 company job boards, updated as roles open and close.
Preparing for this interview
Interviews for analog roles keep coming back to Python, MATLAB. Practise those questions before you sit with Kandou AI.
Questions you are likely to be asked
- Why do you want to join Kandou AI?
- Walk me through a system you built. How was it designed, and what would you change now?
- Tell me about a hard bug you tracked down. How did you find the cause?
- How do you decide what to test, and what does good code review look like to you?
- Describe a time a deadline forced a trade-off in quality. What did you choose and why?
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Practise the Analog Layout Engineer (Lead) at Kandou AI interview free →At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption. Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient . Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale. Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future. Job title: Analog Layout Engineer (Lead) Location: EU/CH/UK Responsibility Position in custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip to chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodes Layout and verification of very high-speed analog circuits Interact closely with the design team to understand requirements and implement solutions Support IP and chip level integration Support and interact with customers on requirements, and IP delivery Exposure to flip-chip package technologies Experience 10-15 years of relevant experience. Must have experience in custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits Must have expertise in layout of high-speed /frequency circuits like amplifiers, oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, buffers, regulators, filters, data converters, etc. Understanding of layout approaches and techniques for high-speed circuits, matching constraints, minimization of parasitics, power grids and ESD requirements Experience on modern semiconductor process technologies including 28nm, 14/16nm, 7nm User of EDA tool for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc. Skills Self-motivated, with strong sense of ownership and responsibility. Good communicator and team player Manage workload and schedules and report to internal management team Background in Semiconductor Physics Education Graduate in E.E. Find more English Speaking Jobs in United Kingdom on Arbeitnow
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Listed on arbeitnow · posted 2026-11-02. ApplySarthi collects openings and links to application pages; the role is advertised by Kandou AI, not by us.