Sr. Manager, Physical Design Engineering, Annapurna Labs

Annapurna Labs, designs custom silicon powering AWS’s cloud infrastructure. Custom SoCs live at the heart of Amazon ML servers — including Inferentia and Trainium Systems — delivering high-performance Basic qualifications: - 5+ years people management leading PD teams of 8+ engineers, including hiring, performance management, and organizational growth. - 10+ years hands-on ASIC/SoC physical design across multiple advanced nodes (7nm, 5nm, 3nm) with multiple successful tapeouts. - Technical depth across full RTL-to-GDSII: floorplanning, CTS, routing, timing closure, PDN design, IR-drop/EM signoff, physical verification, and tapeout. - Mastery of both EDA ecosystems: Synopsys (Fusion Compiler/ICC2, PrimeTime, StarRC, RedHawk-SC) AND Cadence (Innovus, Tempus, Quantus, Voltus). Physical verification with Siemens Calibre (DRC, LVS, PERC). - Deep expertise in advanced STA (MMMC, POCV/AOCV, SSTA, PBA, IR-aware timing) and power integrity (static/dynamic IR-drop, EM, rush current, Ldi/dt, package-aware analysis). - Proven expertise in high-speed PD (multi-GHz datapaths, SerDes, DDR5, HBM, PCIe Gen5+, UCIe) and low-power design (UPF, power gating, DVFS, retention). - Experience with hierarchical methodologies for very large SoCs (>1B transistors). Expert scripting in TCL, Python, Perl. Preferred: - Experience leading PD for AI/ML accelerators, GPUs, or high-performance data-center SoCs at leading semiconductor companies or hyperscalers. - Direct 3nm GAA/Nanosheet experience; 2nm or sub-2nm engagement. Familiarity with CFET and backside power delivery (BSPDN). - Quantifiable track record of continuous PPA improvement and metric-driven flow development across multiple projects and nodes. - Strong program execution: managing concurrent tapeouts, milestone tracking, risk identification, and executive communication. - Hands-on 2.5D/3D integration experience (CoWoS, EMIB, InFO, SoIC, Foveros) and chiplet strategy with UCIe. - Track record deploying AI/ML-driven design methodologies in production flows. - Experience with CPO, HBM4, silicon photonics, or CXL physical design. - Multi-foundry technology assessment experience (TSMC, Samsung, Intel Foundry Services). - Experience managing geographically distributed teams (U.S., Israel, global). - Experience scaling PD organizations through 2x–3x growth. Patent portfolio or industry standards contributions (UCIe, IEEE). Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. As a total compensation company, Amazon's package may include other elements such as sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon offers comprehensive benefits including health insurance (medical, dental, vision, prescription, basic life & AD&D insurance), Registered Retirement Savings Plan (RRSP), Deferred Profit Sharing Plan (DPSP), paid time off, and other resources to improve health and well-being. We thank all applicants for their interest, however only those interviewed will be advised as to hiring status. CAN, ON, Toronto - 207,900.00 - 347,100.00 CAD annually